[1/2] checkasm: arm: Print the differing bits when FPSCR is clobbered

Message ID 1468755038-22472-1-git-send-email-martin@martin.st
State Committed
Headers show

Commit Message

Martin Storsjö July 17, 2016, 11:30 a.m.
---
Changed to use r1 for all of this.
---
 tests/checkasm/arm/checkasm.S | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

Patch

diff --git a/tests/checkasm/arm/checkasm.S b/tests/checkasm/arm/checkasm.S
index 2768bb3..3a7888c 100644
--- a/tests/checkasm/arm/checkasm.S
+++ b/tests/checkasm/arm/checkasm.S
@@ -40,7 +40,7 @@  const register_init, align=3
 endconst
 
 const error_message_fpscr
-    .asciz "failed to preserve register FPSCR"
+    .asciz "failed to preserve register FPSCR, changed bits shifted left by 5: %x"
 error_message_gpr:
     .asciz "failed to preserve register r%d"
 error_message_vfp:
@@ -106,11 +106,11 @@  function checkasm_checked_call_\variant, export=1
 .endr
 .purgem check_reg_vfp
 
-    fmrx        r0,  FPSCR
+    fmrx        r1,  FPSCR
     ldr         r3,  [sp, #8]
-    eor         r0,  r0,  r3
+    eor         r1,  r1,  r3
     @ Ignore changes in the topmost 5 bits
-    lsls        r0,  r0,  #5
+    lsls        r1,  r1,  #5
     bne         3f
 .endif