[2/2] checkasm: arm: Ignore changes to bits 0-4 and 7 to FPSCR
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Message ID 1468755038-22472-2-git-send-email-martin@martin.st
State Committed
Headers show

Commit Message

Martin Storsjö July 17, 2016, 11:30 a.m. 
These bits are set by exceptions in NEON instructions.

Also use bic instead of lsl, for clearing the topmost bits.
---
 tests/checkasm/arm/checkasm.S | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

Comments

Janne Grunau July 17, 2016, 11:48 a.m. | #1 
On 2016-07-17 14:30:38 +0300, Martin Storsjö wrote:
> These bits are set by exceptions in NEON instructions.
> 
> Also use bic instead of lsl, for clearing the topmost bits.
> ---
>  tests/checkasm/arm/checkasm.S | 6 ++++--
>  1 file changed, 4 insertions(+), 2 deletions(-)
> 
> diff --git a/tests/checkasm/arm/checkasm.S b/tests/checkasm/arm/checkasm.S
> index 3a7888c..ab53d0a 100644
> --- a/tests/checkasm/arm/checkasm.S
> +++ b/tests/checkasm/arm/checkasm.S
> @@ -40,7 +40,7 @@ const register_init, align=3
>  endconst
>  
>  const error_message_fpscr
> -    .asciz "failed to preserve register FPSCR, changed bits shifted left by 5: %x"
> +    .asciz "failed to preserve register FPSCR, changed bits: %x"
>  error_message_gpr:
>      .asciz "failed to preserve register r%d"
>  error_message_vfp:
> @@ -109,8 +109,10 @@ function checkasm_checked_call_\variant, export=1
>      fmrx        r1,  FPSCR
>      ldr         r3,  [sp, #8]
>      eor         r1,  r1,  r3
> +    @ Ignore changes in bits 0-4 and 7
> +    bic         r1,  r1,  #0x9f
>      @ Ignore changes in the topmost 5 bits
> -    lsls        r1,  r1,  #5
> +    bics        r1,  r1,  #0xf8000000
>      bne         3f
>  .endif

I was about to send a very similar patch. Feel free to fold both patches 
and both are ok.

Janne

Patch
diff mbox 

diff --git a/tests/checkasm/arm/checkasm.S b/tests/checkasm/arm/checkasm.S
index 3a7888c..ab53d0a 100644
--- a/tests/checkasm/arm/checkasm.S
+++ b/tests/checkasm/arm/checkasm.S
@@ -40,7 +40,7 @@  const register_init, align=3
 endconst
 
 const error_message_fpscr
-    .asciz "failed to preserve register FPSCR, changed bits shifted left by 5: %x"
+    .asciz "failed to preserve register FPSCR, changed bits: %x"
 error_message_gpr:
     .asciz "failed to preserve register r%d"
 error_message_vfp:
@@ -109,8 +109,10 @@  function checkasm_checked_call_\variant, export=1
     fmrx        r1,  FPSCR
     ldr         r3,  [sp, #8]
     eor         r1,  r1,  r3
+    @ Ignore changes in bits 0-4 and 7
+    bic         r1,  r1,  #0x9f
     @ Ignore changes in the topmost 5 bits
-    lsls        r1,  r1,  #5
+    bics        r1,  r1,  #0xf8000000
     bne         3f
 .endif