[PATCHv3] arm: vp9: Add NEON optimizations of VP9 MC functions

Message ID 1476904723-18747-1-git-send-email-martin@martin.st
State Superseded
Headers show

Commit Message

Martin Storsjö Oct. 19, 2016, 7:18 p.m.
This work is sponsored by, and copyright, Google.

The filter coefficients are signed values, where the product of the
multiplication with one individual filter coefficient doesn't
overflow a 16 bit signed value (the largest filter coefficient is
127). But when the products are accumulated, the resulting sum can
overflow the 16 bit signed range. Instead of accumulating in 32 bit,
we accumulate all filter taps but the largest one in one register, and
the largest one (either index 3 or 4) in a separate one, added with
saturation afterwards.

(The VP8 MC asm does something similar, but slightly simpler, by
accumulating each half of the filter separately. In the VP9 MC
filters, each half of the filter can also overflow though, so the
largest component has to be handled individually.)

Examples of relative speedup compared to the C version, from checkasm:
                       Cortex      A7     A8     A9    A53
vp9_avg4_neon:                   1.63   1.19   1.37   1.54
vp9_avg8_neon:                   2.24   3.65   3.30   2.56
vp9_avg16_neon:                  2.64   6.72   2.92   2.80
vp9_avg32_neon:                  2.50   5.45   2.76   2.45
vp9_avg64_neon:                  2.69   5.81   2.72   2.79
vp9_avg_8tap_smooth_4h_neon:     3.29   4.71   2.90   4.78
vp9_avg_8tap_smooth_4hv_neon:    3.78   4.54   3.33   4.51
vp9_avg_8tap_smooth_4v_neon:     5.18   6.52   4.29   5.50
vp9_avg_8tap_smooth_8h_neon:     6.47   9.07   5.47   9.66
vp9_avg_8tap_smooth_8hv_neon:    6.60   8.16   5.98   7.91
vp9_avg_8tap_smooth_8v_neon:     9.25  12.67   8.07   9.61
vp9_avg_8tap_smooth_64h_neon:    6.98  10.36   5.91  11.59
vp9_avg_8tap_smooth_64hv_neon:   6.39   9.15   6.05   8.48
vp9_avg_8tap_smooth_64v_neon:   10.64  14.12   9.39  11.05
vp9_put4_neon:                   1.30   1.15   0.89   1.35
vp9_put8_neon:                   1.28   2.07   1.80   1.62
vp9_put16_neon:                  1.64   4.08   1.71   1.93
vp9_put32_neon:                  1.53   3.68   2.12   1.68
vp9_put64_neon:                  2.01   3.98   1.91   1.91
vp9_put_8tap_smooth_4h_neon:     3.05   4.47   2.68   4.53
vp9_put_8tap_smooth_4hv_neon:    3.74   4.46   3.31   4.50
vp9_put_8tap_smooth_4v_neon:     5.23   6.19   4.28   5.87
vp9_put_8tap_smooth_8h_neon:     5.89   8.40   4.97   8.99
vp9_put_8tap_smooth_8hv_neon:    6.84   8.05   5.90   7.91
vp9_put_8tap_smooth_8v_neon:     9.41  11.97   7.99  10.49
vp9_put_8tap_smooth_64h_neon:    6.61   9.79   5.06  11.35
vp9_put_8tap_smooth_64hv_neon:   7.01   9.13   6.37   9.17
vp9_put_8tap_smooth_64v_neon:   11.09  13.31   9.32  12.52

For the larger 8tap filters, the speedup vs C code is around 6-14x.

This is significantly faster than libvpx's implementation of the same
functions, at least when comparing the put_8tap_smooth_64 functions
(compared to vpx_convolve8_horiz_neon and vpx_convolve8_vert_neon from
libvpx).

Absolute runtimes from checkasm:
                          Cortex      A7        A8        A9       A53
vp9_put_8tap_smooth_64h_neon:    21229.8   14474.5   19790.1   10885.1
libvpx vpx_convolve8_horiz_neon: 52623.3   19736.4   21907.7   25027.7

vp9_put_8tap_smooth_64v_neon:    14966.6   12297.2   13786.5   11679.4
libvpx vpx_convolve8_vert_neon:  42090.0   17706.2   17659.9   16941.2

Thus, on the A9, the horizontal filter is only marginally faster than
libvpx, while our version is significantly faster on the other cores,
and the vertical filter is significantly faster on all cores. The
difference is especially large on the A7.

The libvpx implementation does the accumulation in 32 bit, which
probably explains most the differences.
---
v3: Adjusted the edge_emu_buffer size and the condition for invoking
edge emu; this part was OK'd by Ronald on irc. In a quick test on x86,
it didn't affect the total decoding time significantly (within
measurement noise).

v2: Since the previous version, I tuned the avg4 and put4 a bit further,
making avg4 faster than C on the A8, and improving put4 a little on A7
and A53. put4 is still marginally slower than the C version on A9 though,
but I think it isn't worth the trouble to try to workaround it.

Rewrapped some paragraphs in the commit message, that were unnecessarily
narrow. Changed the big benchmark table into one with relative speedups.
---
 libavcodec/arm/Makefile          |   2 +
 libavcodec/arm/vp9dsp_init_arm.c | 140 +++++++
 libavcodec/arm/vp9mc_neon.S      | 787 +++++++++++++++++++++++++++++++++++++++
 libavcodec/vp9.h                 |   4 +-
 libavcodec/vp9block.c            |  10 +-
 libavcodec/vp9dsp.c              |   2 +
 6 files changed, 942 insertions(+), 3 deletions(-)
 create mode 100644 libavcodec/arm/vp9dsp_init_arm.c
 create mode 100644 libavcodec/arm/vp9mc_neon.S

Comments

Janne Grunau Nov. 1, 2016, 11:50 p.m. | #1
On 2016-10-19 22:18:43 +0300, Martin Storsjö wrote:
> This work is sponsored by, and copyright, Google.
> 
> The filter coefficients are signed values, where the product of the
> multiplication with one individual filter coefficient doesn't
> overflow a 16 bit signed value (the largest filter coefficient is
> 127). But when the products are accumulated, the resulting sum can
> overflow the 16 bit signed range. Instead of accumulating in 32 bit,
> we accumulate all filter taps but the largest one in one register, and
> the largest one (either index 3 or 4) in a separate one, added with
> saturation afterwards.

"Instead of ..., we accumulate the largest product (either index 3 or 4)
last with a saturated addition."

Is shorter and easier to understand.

...

> ---
>  libavcodec/arm/Makefile          |   2 +
>  libavcodec/arm/vp9dsp_init_arm.c | 140 +++++++
>  libavcodec/arm/vp9mc_neon.S      | 787 +++++++++++++++++++++++++++++++++++++++
>  libavcodec/vp9.h                 |   4 +-
>  libavcodec/vp9block.c            |  10 +-
>  libavcodec/vp9dsp.c              |   2 +
>  6 files changed, 942 insertions(+), 3 deletions(-)
>  create mode 100644 libavcodec/arm/vp9dsp_init_arm.c
>  create mode 100644 libavcodec/arm/vp9mc_neon.S
> 
> diff --git a/libavcodec/arm/Makefile b/libavcodec/arm/Makefile
> index bd4dd4e..2638230 100644
> --- a/libavcodec/arm/Makefile
> +++ b/libavcodec/arm/Makefile
> @@ -45,6 +45,7 @@ OBJS-$(CONFIG_MLP_DECODER)             += arm/mlpdsp_init_arm.o
>  OBJS-$(CONFIG_RV40_DECODER)            += arm/rv40dsp_init_arm.o
>  OBJS-$(CONFIG_VORBIS_DECODER)          += arm/vorbisdsp_init_arm.o
>  OBJS-$(CONFIG_VP6_DECODER)             += arm/vp6dsp_init_arm.o
> +OBJS-$(CONFIG_VP9_DECODER)             += arm/vp9dsp_init_arm.o
>  
>  
>  # ARMv5 optimizations
> @@ -138,3 +139,4 @@ NEON-OBJS-$(CONFIG_RV40_DECODER)       += arm/rv34dsp_neon.o            \
>                                            arm/rv40dsp_neon.o
>  NEON-OBJS-$(CONFIG_VORBIS_DECODER)     += arm/vorbisdsp_neon.o
>  NEON-OBJS-$(CONFIG_VP6_DECODER)        += arm/vp6dsp_neon.o
> +NEON-OBJS-$(CONFIG_VP9_DECODER)        += arm/vp9mc_neon.o
> diff --git a/libavcodec/arm/vp9dsp_init_arm.c b/libavcodec/arm/vp9dsp_init_arm.c
> new file mode 100644
> index 0000000..db8c683
> --- /dev/null
> +++ b/libavcodec/arm/vp9dsp_init_arm.c
> @@ -0,0 +1,140 @@
> +/*
> + * Copyright (c) 2016 Google Inc.
> + *
> + * This file is part of Libav.
> + *
> + * Libav is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU Lesser General Public
> + * License as published by the Free Software Foundation; either
> + * version 2.1 of the License, or (at your option) any later version.
> + *
> + * Libav is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
> + * Lesser General Public License for more details.
> + *
> + * You should have received a copy of the GNU Lesser General Public
> + * License along with Libav; if not, write to the Free Software
> + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
> + */
> +
> +#include <stdint.h>
> +
> +#include "libavutil/attributes.h"
> +#include "libavutil/arm/cpu.h"
> +#include "libavcodec/vp9.h"
> +
> +#define declare_fpel(type, sz)                                          \
> +void ff_vp9_##type##sz##_neon(uint8_t *dst, ptrdiff_t dst_stride,       \
> +                              const uint8_t *src, ptrdiff_t src_stride, \
> +                              int h, int mx, int my)
> +
> +#define declare_copy_avg(sz) \
> +    declare_fpel(copy, sz);  \
> +    declare_fpel(avg , sz)
> +
> +#define decl_mc_func(op, filter, dir, sz)                                                \
> +void ff_vp9_##op##_##filter##sz##_##dir##_neon(uint8_t *dst, ptrdiff_t dst_stride,       \
> +                                               const uint8_t *src, ptrdiff_t src_stride, \
> +                                               int h, int mx, int my)
> +
> +#define define_8tap_2d_fn(op, filter, sz)                                         \
> +static void op##_##filter##sz##_hv_neon(uint8_t *dst, ptrdiff_t dst_stride,       \
> +                                        const uint8_t *src, ptrdiff_t src_stride, \
> +                                        int h, int mx, int my)                    \
> +{                                                                                 \
> +    LOCAL_ALIGNED_16(uint8_t, temp, [72 * 64]);                                   \

Is there a reason why the temporary array doesn't depend on the size?

> +    /* We only need h + 7 lines, but the horizontal filter assumes an             \
> +     * even number of rows, so filter h + 8 lines here. */                        \
> +    ff_vp9_put_##filter##sz##_h_neon(temp, 64,                                    \
> +                                     src - 3 * src_stride, src_stride,            \
> +                                     h + 8, mx, 0);                               \
> +    ff_vp9_##op##_##filter##sz##_v_neon(dst, dst_stride,                          \
> +                                        temp + 3 * 64, 64,                        \
> +                                        h, 0, my);                                \

I guess you haven't tried implementing the diagonal mc fully in asm?
Probably not worth the effort since the only significant gain comes from
keeping the temporary values in registers which works on size 4 and 8 and
maybe 16 for aarch64 wich are probably not that important.

...

> diff --git a/libavcodec/arm/vp9mc_neon.S b/libavcodec/arm/vp9mc_neon.S
> new file mode 100644
> index 0000000..754ac50
> --- /dev/null
> +++ b/libavcodec/arm/vp9mc_neon.S
> @@ -0,0 +1,787 @@

...

> +@ All public functions in this file have the following signature:
> +@ typedef void (*vp9_mc_func)(uint8_t *dst, ptrdiff_t dst_stride,
> +@                            const uint8_t *ref, ptrdiff_t ref_stride,
> +@                            int h, int mx, int my);
> +
> +function ff_vp9_copy64_neon, export=1
> +        ldr             r12, [sp]
> +        sub             r1,  r1,  #48
> +        sub             r3,  r3,  #48
> +1:
> +        vld1.8          {q0},  [r2]!
> +        vld1.8          {q1},  [r2]!
> +        vst1.8          {q0},  [r0, :128]!
> +        vld1.8          {q2},  [r2]!
> +        vst1.8          {q1},  [r0, :128]!
> +        vld1.8          {q3},  [r2], r3
> +        vst1.8          {q2},  [r0, :128]!
> +        subs            r12, r12, #1
> +        vst1.8          {q3},  [r0, :128], r1
> +        bne             1b
> +        bx              lr
> +endfunc
> +
> +function ff_vp9_avg64_neon, export=1
> +        ldr             r12, [sp]
> +        sub             r1,  r1,  #48
> +        sub             r3,  r3,  #48
> +1:
> +        vld1.8          {q8},  [r2]!
> +        vld1.8          {q0},  [r0, :128]!
> +        vld1.8          {q9},  [r2]!
> +        vld1.8          {q1},  [r0, :128]!
> +        vrhadd.u8       q0,  q0,  q8
> +        vld1.8          {q10}, [r2]!
> +        vld1.8          {q2},  [r0, :128]!
> +        vrhadd.u8       q1,  q1,  q9
> +        vld1.8          {q11}, [r2], r3
> +        vld1.8          {q3},  [r0, :128]
> +        vrhadd.u8       q2,  q2,  q10
> +        sub             r0,  r0,  #48

using an additional register for writing to dst proabably makes sense

> +        vrhadd.u8       q3,  q3,  q11
> +        vst1.8          {q0},  [r0, :128]!
> +        vst1.8          {q1},  [r0, :128]!
> +        vst1.8          {q2},  [r0, :128]!
> +        vst1.8          {q3},  [r0, :128], r1
> +        subs            r12, r12, #1
> +        bne             1b
> +        bx              lr
> +endfunc

Have you tried 4 d-register loads/stores? If it's not slower it's
preferable since it uses less instructions. Same for size 32 with the
additional advantange of not having to adjust the stride

> +
> +function ff_vp9_copy32_neon, export=1
> +        ldr             r12, [sp]
> +        sub             r1,  r1,  #16
> +        sub             r3,  r3,  #16
> +1:
> +        vld1.8          {q0},  [r2]!
> +        vst1.8          {q0},  [r0, :128]!
> +        subs            r12, r12, #1
> +        vld1.8          {q1},  [r2], r3
> +        vst1.8          {q1},  [r0, :128], r1
> +        bne             1b
> +        bx              lr
> +endfunc
> +
> +function ff_vp9_avg32_neon, export=1
> +        ldr             r12, [sp]
> +        sub             r1,  r1,  #16
> +        sub             r3,  r3,  #16
> +1:
> +        vld1.8          {q2},  [r2]!
> +        vld1.8          {q0},  [r0, :128]!
> +        vld1.8          {q3},  [r2], r3
> +        vrhadd.u8       q0,  q0,  q2
> +        vld1.8          {q1},  [r0, :128]
> +        vrhadd.u8       q1,  q1,  q3
> +        sub             r0,  r0,  #16

32-byte load for dst will leave r0 unmodified

> +        vst1.8          {q0},  [r0, :128]!
> +        vst1.8          {q1},  [r0, :128], r1
> +        subs            r12, r12, #1
> +        bne             1b
> +        bx              lr
> +endfunc
> +
> +function ff_vp9_copy16_neon, export=1
> +        ldr             r12, [sp]
> +        push            {r4-r5}
> +        add             r4,  r0,  r1
> +        add             r5,  r2,  r3
> +        add             r1,  r1,  r1
> +        add             r3,  r3,  r3
> +1:
> +        vld1.8          {q0},  [r2], r3
> +        vld1.8          {q1},  [r5], r3
> +        subs            r12, r12, #2
> +        vst1.8          {q0},  [r0, :128], r1
> +        vst1.8          {q1},  [r4, :128], r1
> +        bne             1b
> +        pop             {r4-r5}
> +        bx              lr
> +endfunc
> +
> +function ff_vp9_avg16_neon, export=1
> +        ldr             r12, [sp]
> +1:
> +        vld1.8          {q2},  [r2], r3
> +        vld1.8          {q0},  [r0, :128], r1
> +        vld1.8          {q3},  [r2], r3
> +        vrhadd.u8       q0,  q0,  q2
> +        vld1.8          {q1},  [r0, :128]
> +        sub             r0,  r0,  r1

have you tried storing q0 with writeback and then loading q1?

> +        vrhadd.u8       q1,  q1,  q3
> +        subs            r12, r12, #2
> +        vst1.8          {q0},  [r0, :128], r1
> +        vst1.8          {q1},  [r0, :128], r1
> +        bne             1b
> +        bx              lr
> +endfunc
> +
> +function ff_vp9_copy8_neon, export=1
> +        ldr             r12, [sp]
> +1:
> +        vld1.8          {d0},  [r2], r3
> +        vld1.8          {d1},  [r2], r3
> +        subs            r12, r12, #2
> +        vst1.8          {d0},  [r0, :64], r1
> +        vst1.8          {d1},  [r0, :64], r1
> +        bne             1b
> +        bx              lr
> +endfunc
> +
> +function ff_vp9_avg8_neon, export=1
> +        ldr             r12, [sp]
> +1:
> +        vld1.8          {d2},  [r2], r3
> +        vld1.8          {d0},  [r0, :64], r1
> +        vld1.8          {d3},  [r2], r3
> +        vrhadd.u8       d0,  d0,  d2
> +        vld1.8          {d1},  [r0, :64]
> +        sub             r0,  r0,  r1

same as 16 although it's probably silly for size 8, using an additional
register would the other possibility to speed it up

> +        vrhadd.u8       d1,  d1,  d3
> +        subs            r12, r12, #2
> +        vst1.8          {d0},  [r0, :64], r1
> +        vst1.8          {d1},  [r0, :64], r1
> +        bne             1b
> +        bx              lr
> +endfunc
> +
> +function ff_vp9_copy4_neon, export=1
> +        ldr             r12, [sp]
> +1:
> +        vld1.32         {d0[]},   [r2], r3
> +        vld1.32         {d1[]},   [r2], r3
> +        vst1.32         {d0[0]},  [r0, :32], r1
> +        vld1.32         {d2[]},   [r2], r3
> +        vst1.32         {d1[0]},  [r0, :32], r1
> +        vld1.32         {d3[]},   [r2], r3
> +        subs            r12, r12, #4
> +        vst1.32         {d2[0]},  [r0, :32], r1
> +        vst1.32         {d3[0]},  [r0, :32], r1
> +        bne             1b
> +        bx              lr
> +endfunc
> +
> +function ff_vp9_avg4_neon, export=1
> +        ldr             r12, [sp]
> +1:
> +        vld1.32         {d4[]},   [r2], r3
> +        vld1.32         {d0[]},   [r0, :32], r1
> +        vld1.32         {d5[]},   [r2], r3
> +        vrhadd.u8       d0,  d0,  d4
> +        vld1.32         {d1[]},   [r0, :32], r1
> +        vld1.32         {d6[]},   [r2], r3
> +        vrhadd.u8       d1,  d1,  d5
> +        vld1.32         {d2[]},   [r0, :32], r1
> +        vld1.32         {d7[]},   [r2], r3
> +        vrhadd.u8       d2,  d2,  d6
> +        vld1.32         {d3[]},   [r0, :32], r1
> +        sub             r0,  r0,  r1, lsl #2
> +        subs            r12, r12, #4
> +        vst1.32         {d0[0]},  [r0, :32], r1
> +        vrhadd.u8       d3,  d3,  d7
> +        vst1.32         {d1[0]},  [r0, :32], r1
> +        vst1.32         {d2[0]},  [r0, :32], r1
> +        vst1.32         {d3[0]},  [r0, :32], r1
> +        bne             1b
> +        bx              lr
> +endfunc

...

> +@ Instantiate a horizontal filter function for the given size.
> +@ This can work on 4, 8 or 16 pixels in parallel; for larger
> +@ widths it will do 16 pixels at a time and loop horizontally.
> +@ The actual width is passed in r12, and the height in r4.
> +@ idx2 is the index of the largest filter coefficient (3 or 4)
> +@ and idx1 is the other one of them.
> +.macro do_8tap_h type, size, idx1, idx2
> +function \type\()_8tap_\size\()h_\idx1\idx2
> +        sub             r2,  r2,  #3
> +        add             r6,  r0,  r1
> +        add             r7,  r2,  r3
> +        add             r1,  r1,  r1
> +        add             r3,  r3,  r3
> +        @ Only size > 16 loops horizontally and needs
> +        @ reduced dst stride
> +.if \size > 16
> +        sub             r1,  r1,  r12
> +.endif
> +        @ size >= 16 loads two qwords and increments r2,
> +        @ for size 4/8 it's enough with one qword and no
> +        @ postincrement
> +.if \size >= 16
> +        sub             r3,  r3,  r12
> +        sub             r3,  r3,  #8
> +.endif
> +        @ Load the filter vector
> +        vld1.16         {q0},  [r5,:128]
> +1:
> +.if \size > 16
> +        mov             r5,  r12
> +.endif
> +        @ Load src
> +.if \size >= 16
> +        vld1.8          {q8},  [r2]!
> +        vld1.8          {q11}, [r7]!
> +        vld1.8          {d20}, [r2]!
> +        vld1.8          {d26}, [r7]!
> +.else
> +        vld1.8          {q8},  [r2]
> +        vld1.8          {q11}, [r7]
> +.endif
> +        vmovl.u8        q9,  d17
> +        vmovl.u8        q8,  d16
> +        vmovl.u8        q12, d23
> +        vmovl.u8        q11, d22
> +.if \size >= 16
> +        vmovl.u8        q10, d20
> +        vmovl.u8        q13, d26
> +.endif
> +2:
> +
> +        @ Accumulate, adding idx2 last with a separate
> +        @ saturating add. The positive filter coefficients
> +        @ for all indices except idx2 must add up to less
> +        @ than 127 for this not to overflow.
> +        vmul.s16        q1,  q8,  d0[0]
> +        vmul.s16        q3,  q11, d0[0]
> +.if \size >= 16
> +        vmul.s16        q2,  q9,  d0[0]
> +        vmul.s16        q4,  q12, d0[0]
> +.endif
> +        extmla          q1,  q2,  q3,  q4,  q8,  q9,  q10,  q11, q12, q13, 1,     \size
> +        extmla          q1,  q2,  q3,  q4,  q8,  q9,  q10,  q11, q12, q13, 2,     \size
> +        extmla          q1,  q2,  q3,  q4,  q8,  q9,  q10,  q11, q12, q13, \idx1, \size
> +        extmla          q1,  q2,  q3,  q4,  q8,  q9,  q10,  q11, q12, q13, 5,     \size
> +        extmla          q1,  q2,  q3,  q4,  q8,  q9,  q10,  q11, q12, q13, 6,     \size
> +        extmla          q1,  q2,  q3,  q4,  q8,  q9,  q10,  q11, q12, q13, 7,     \size
> +        extmulqadd      q1,  q2,  q3,  q4,  q8,  q9,  q10,  q11, q12, q13, \idx2, \size
> +
> +        @ Round, shift and saturate
> +        vqrshrun.s16    d2,  q1,  #7
> +        vqrshrun.s16    d6,  q3,  #7
> +.if \size >= 16
> +        vqrshrun.s16    d3,  q2,  #7
> +        vqrshrun.s16    d7,  q4,  #7
> +.endif
> +        @ Average
> +.ifc \type,avg
> +.if \size >= 16
> +        vld1.8          {q14}, [r0,:128]
> +        vld1.8          {q15}, [r6,:128]
> +        vrhadd.u8       q1,  q1,  q14
> +        vrhadd.u8       q3,  q3,  q15
> +.elseif \size == 8
> +        vld1.8          {d28}, [r0,:64]
> +        vld1.8          {d30}, [r6,:64]
> +        vrhadd.u8       d2,  d2,  d28
> +        vrhadd.u8       d6,  d6,  d30
> +.else
> +        @ We only need d28[0], but [] is faster on some cores
> +        vld1.32         {d28[]}, [r0,:32]
> +        vld1.32         {d30[]}, [r6,:32]
> +        vrhadd.u8       d2,  d2,  d28
> +        vrhadd.u8       d6,  d6,  d30
> +.endif
> +.endif
> +        @ Store and loop horizontally (for size > 16)
> +.if \size > 16
> +        vst1.8          {q1}, [r0,:128]!
> +        vst1.8          {q3}, [r6,:128]!
> +        vmov            q8,  q10
> +        vmov            q11, q13
> +        subs            r5,  r5,  #16
> +        beq             3f
> +        vld1.8          {q10}, [r2]!
> +        vld1.8          {q13}, [r7]!
> +        vmovl.u8        q9,  d20
> +        vmovl.u8        q10, d21
> +        vmovl.u8        q12, d26
> +        vmovl.u8        q13, d27
> +        b               2b
> +.elseif \size == 16
> +        vst1.8          {q1}, [r0,:128]
> +        vst1.8          {q3}, [r6,:128]
> +.elseif \size == 8
> +        vst1.8          {d2}, [r0,:64]
> +        vst1.8          {d6}, [r6,:64]
> +.else @ \size == 4
> +        vst1.32         {d2[0]}, [r0,:32]
> +        vst1.32         {d6[0]}, [r6,:32]
> +.endif
> +3:
> +        @ Loop vertically
> +        add             r0,  r0,  r1
> +        add             r6,  r6,  r1
> +        add             r2,  r2,  r3
> +        add             r7,  r7,  r3
> +        subs            r4,  r4,  #2
> +        bne             1b
> +.if \size >= 16
> +        vpop            {q4-q6}
> +.endif
> +        pop             {r4-r7}
> +        bx              lr
> +endfunc
> +.endm
> +
> +.macro do_8tap_h_size size
> +do_8tap_h put, \size, 3, 4
> +do_8tap_h avg, \size, 3, 4
> +do_8tap_h put, \size, 4, 3
> +do_8tap_h avg, \size, 4, 3
> +.endm
> +
> +do_8tap_h_size 4
> +do_8tap_h_size 8
> +do_8tap_h_size 16
> +do_8tap_h_size 32

I'm not sure if it's worth to have the size 32+ version. The additional
loop checks are probably not noticeable in size 16 case and it would
reduce the binary size.

The other idea for keeping the calculation in signed 16-bit would have
been using a negative constant as offset since the range doesn't exceed
16-bit. Not faster in checkasm but smaller binary size.

No need to try that. Current implementation is fine for me and looks
quite nice.

...

> +@ Vertical filters

...

> +@ Evaluate the filter twice in parallel, from the inputs src1-src9 
> into dst1-dst2
> +@ (src1-src8 into dst1, src2-src9 into dst2), adding idx2 separately
> +@ at the end with saturation
> +.macro convolve dst1, dst2, src1, src2, src3, src4, src5, src6, src7, src8, src9, idx1, idx2, tmp1, tmp2
> +        vmul.s16        \dst1, \src1, d0[0]
> +        vmul.s16        \dst2, \src2, d0[0]
> +        vmla.s16        \dst1, \src2, d0[1]
> +        vmla.s16        \dst2, \src3, d0[1]
> +        vmla.s16        \dst1, \src3, d0[2]
> +        vmla.s16        \dst2, \src4, d0[2]
> +.if \idx1 == 3
> +        vmla.s16        \dst1, \src4, d0[3]
> +        vmla.s16        \dst2, \src5, d0[3]
> +.else
> +        vmla.s16        \dst1, \src5, d1[0]
> +        vmla.s16        \dst2, \src6, d1[0]
> +.endif
> +        vmla.s16        \dst1, \src6, d1[1]
> +        vmla.s16        \dst2, \src7, d1[1]
> +        vmla.s16        \dst1, \src7, d1[2]
> +        vmla.s16        \dst2, \src8, d1[2]
> +        vmla.s16        \dst1, \src8, d1[3]
> +        vmla.s16        \dst2, \src9, d1[3]
> +.if \idx2 == 3
> +        vmul.s16        \tmp1, \src4, d0[3]
> +        vmul.s16        \tmp2, \src5, d0[3]
> +.else
> +        vmul.s16        \tmp1, \src5, d1[0]
> +        vmul.s16        \tmp2, \src6, d1[0]
> +.endif
> +        vqadd.s16       \dst1, \dst1, \tmp1
> +        vqadd.s16       \dst2, \dst2, \tmp2
> +.endm

the negative terms could be accumulated in tmp1/2 I doubt it makes a
difference in practice but reduces data dependencies.

...

> +@ Instantiate a vertical filter function for filtering a 4 pixels 
> wide
> +@ slice. The first half of the registers contain one row, while the second
> +@ half of a register contains the second-next row (also stored in the first
> +@ half of the register two steps ahead). The convolution does two outputs
> +@ at a time; the output of q5-q12 into one, and q4-q13 into another one.
> +@ The first half of first output is the first output row, the first half
> +@ of the other output is the second output row. The second halves of the
> +@ registers are rows 3 and 4.
> +@ This only is designed to work for 4 or 8 output lines.
> +.macro do_8tap_4v type, idx1, idx2
> +function \type\()_8tap_4v_\idx1\idx2
> +        sub             r2,  r2,  r3, lsl #1
> +        sub             r2,  r2,  r3
> +        vld1.16         {q0},  [r12, :128]
> +
> +        vld1.32         {d2[]},   [r2], r3
> +        vld1.32         {d3[]},   [r2], r3
> +        vld1.32         {d4[]},   [r2], r3
> +        vld1.32         {d5[]},   [r2], r3
> +        vld1.32         {d6[]},   [r2], r3
> +        vld1.32         {d7[]},   [r2], r3
> +        vld1.32         {d8[]},   [r2], r3
> +        vld1.32         {d9[]},   [r2], r3
> +        vld1.32         {d28[]},  [r2]
> +        sub             r2,  r2,  r3, lsl #2
> +        sub             r2,  r2,  r3, lsl #1
> +        vld1.32         {d2[1]},  [r2], r3

vext.8 d2,  d2,  d4,  #4 should be faster than loading. it works since
we loaded data to all lanes

> +        vld1.32         {d3[1]},  [r2], r3
> +        vmovl.u8        q5,  d2
> +        vld1.32         {d4[1]},  [r2], r3
> +        vmovl.u8        q6,  d3
> +        vld1.32         {d5[1]},  [r2], r3
> +        vmovl.u8        q7,  d4
> +        vld1.32         {d6[1]},  [r2], r3
> +        vmovl.u8        q8,  d5
> +        vld1.32         {d7[1]},  [r2], r3
> +        vmovl.u8        q9,  d6
> +        vld1.32         {d8[1]},  [r2], r3
> +        vmovl.u8        q10, d7
> +        vld1.32         {d9[1]},  [r2], r3
> +        vmovl.u8        q11, d8
> +        vld1.32         {d28[1]}, [r2]
> +        sub             r2,  r2,  r3
> +
> +        vmovl.u8        q12, d9
> +        vmovl.u8        q13, d28
> +
> +        convolve        q1,  q2,  q5,  q6,  q7,  q8,  q9,  q10, q11, q12, q13, \idx1, \idx2, q4, q3
> +        do_store4       q1,  d2,  q2,  d4,  d3,  d5,  \type
> +        subs            r4,  r4,  #4
> +        beq             9f
> +
> +        vld1.32         {d2[]},   [r2], r3
> +        vld1.32         {d3[]},   [r2], r3
> +        vld1.32         {d4[]},   [r2], r3
> +        vld1.32         {d5[]},   [r2], r3
> +        sub             r2,  r2,  r3, lsl #1
> +        vld1.32         {d2[1]},  [r2], r3
> +        vld1.32         {d3[1]},  [r2], r3
> +        vmovl.u8        q14, d2
> +        vld1.32         {d4[1]},  [r2], r3
> +        vmovl.u8        q15, d3
> +        vld1.32         {d5[1]},  [r2], r3
> +        vmovl.u8        q5,  d4
> +        vmovl.u8        q6,  d5
> +
> +        convolve        q1,  q2,  q9,  q10, q11, q12, q13, q14, q15, q5,  q6,  \idx1, \idx2, q4, q3
> +        do_store4       q1,  d2,  q2,  d4,  d3,  d5,  \type
> +
> +9:
> +        vpop            {q4-q7}
> +        pop             {r4-r5}
> +        bx              lr
> +endfunc
> +.endm
> +
> +do_8tap_4v put, 3, 4
> +do_8tap_4v put, 4, 3
> +do_8tap_4v avg, 3, 4
> +do_8tap_4v avg, 4, 3
> +
> +.macro do_8tap_v_func type, filter, size
> +function ff_vp9_\type\()_\filter\()\size\()_v_neon, export=1
> +        push            {r4-r5}
> +        vpush           {q4-q7}
> +        ldr             r4,  [sp, #72]
> +        ldr             r5,  [sp, #80]
> +        movrel          r12, \filter\()_filter-16
> +        add             r12,  r12, r5, lsl #4
> +        cmp             r5,  #8
> +        mov             r5,  #\size

a little confusing that this changes r5 and r12 compared to the
horizontal mc, changing the horizontal mc so that r5 holds the width
and r12 the filter constants/tmp reg would work if you care

Skipped parts are ok and the asm looks already good. Sorry the review 
too so long.

Janne
Martin Storsjö Nov. 2, 2016, 11:11 a.m. | #2
On Wed, 2 Nov 2016, Janne Grunau wrote:

> On 2016-10-19 22:18:43 +0300, Martin Storsjö wrote:
>> This work is sponsored by, and copyright, Google.
>>
>> The filter coefficients are signed values, where the product of the
>> multiplication with one individual filter coefficient doesn't
>> overflow a 16 bit signed value (the largest filter coefficient is
>> 127). But when the products are accumulated, the resulting sum can
>> overflow the 16 bit signed range. Instead of accumulating in 32 bit,
>> we accumulate all filter taps but the largest one in one register, and
>> the largest one (either index 3 or 4) in a separate one, added with
>> saturation afterwards.
>
> "Instead of ..., we accumulate the largest product (either index 3 or 4)
> last with a saturated addition."
>
> Is shorter and easier to understand.

Thanks, amended.

>> +#define define_8tap_2d_fn(op, filter, sz)                                         \
>> +static void op##_##filter##sz##_hv_neon(uint8_t *dst, ptrdiff_t dst_stride,       \
>> +                                        const uint8_t *src, ptrdiff_t src_stride, \
>> +                                        int h, int mx, int my)                    \
>> +{                                                                                 \
>> +    LOCAL_ALIGNED_16(uint8_t, temp, [72 * 64]);                                   \
>
> Is there a reason why the temporary array doesn't depend on the size?

Mostly for simplicity. But I guess it is more efficient to not make it 
larger than necessary and using a tighter stride; fixed.

>> +    /* We only need h + 7 lines, but the horizontal filter assumes an             \
>> +     * even number of rows, so filter h + 8 lines here. */                        \
>> +    ff_vp9_put_##filter##sz##_h_neon(temp, 64,                                    \
>> +                                     src - 3 * src_stride, src_stride,            \
>> +                                     h + 8, mx, 0);                               \
>> +    ff_vp9_##op##_##filter##sz##_v_neon(dst, dst_stride,                          \
>> +                                        temp + 3 * 64, 64,                        \
>> +                                        h, 0, my);                                \
>
> I guess you haven't tried implementing the diagonal mc fully in asm?
> Probably not worth the effort since the only significant gain comes from
> keeping the temporary values in registers which works on size 4 and 8 and
> maybe 16 for aarch64 wich are probably not that important.

I didn't try that fully, no. I did try an asm frontend just like this one, 
though, to avoid a separate vpush/vpop in each of them, and while it does 
save a little, I had to restructure the end of the filter function, which 
cost a little for the plain-horizontal/vertical functions. All in all I 
guess it would be a gain, but not really worth it I think. Being able to 
keep all the intermediates in registers would probably make it more 
worthwhile, but that would also be even more effort. Since you need 7 more 
rows than the actual input size, and the height can be width*2, I think it 
would be hard to keep the intermediates for anything more than size 4 in 
registers even if you'd do a handmade version for it.

>> +function ff_vp9_copy64_neon, export=1
>> +        ldr             r12, [sp]
>> +        sub             r1,  r1,  #48
>> +        sub             r3,  r3,  #48
>> +1:
>> +        vld1.8          {q0},  [r2]!
>> +        vld1.8          {q1},  [r2]!
>> +        vst1.8          {q0},  [r0, :128]!
>> +        vld1.8          {q2},  [r2]!
>> +        vst1.8          {q1},  [r0, :128]!
>> +        vld1.8          {q3},  [r2], r3
>> +        vst1.8          {q2},  [r0, :128]!
>> +        subs            r12, r12, #1
>> +        vst1.8          {q3},  [r0, :128], r1
>> +        bne             1b
>> +        bx              lr
>> +endfunc
>> +
>> +function ff_vp9_avg64_neon, export=1
>> +        ldr             r12, [sp]
>> +        sub             r1,  r1,  #48
>> +        sub             r3,  r3,  #48
>> +1:
>> +        vld1.8          {q8},  [r2]!
>> +        vld1.8          {q0},  [r0, :128]!
>> +        vld1.8          {q9},  [r2]!
>> +        vld1.8          {q1},  [r0, :128]!
>> +        vrhadd.u8       q0,  q0,  q8
>> +        vld1.8          {q10}, [r2]!
>> +        vld1.8          {q2},  [r0, :128]!
>> +        vrhadd.u8       q1,  q1,  q9
>> +        vld1.8          {q11}, [r2], r3
>> +        vld1.8          {q3},  [r0, :128]
>> +        vrhadd.u8       q2,  q2,  q10
>> +        sub             r0,  r0,  #48
>
> using an additional register for writing to dst proabably makes sense

Yes, that helped a little, to avoid the rewind of r0 here

>> +        vrhadd.u8       q3,  q3,  q11
>> +        vst1.8          {q0},  [r0, :128]!
>> +        vst1.8          {q1},  [r0, :128]!
>> +        vst1.8          {q2},  [r0, :128]!
>> +        vst1.8          {q3},  [r0, :128], r1
>> +        subs            r12, r12, #1
>> +        bne             1b
>> +        bx              lr
>> +endfunc
>
> Have you tried 4 d-register loads/stores? If it's not slower it's
> preferable since it uses less instructions. Same for size 32 with the
> additional advantange of not having to adjust the stride

Oh, why didn't I remember those instructions? Yes, this gives a huge gain, 
like a 20% speedup in the 32/64 functions. Thanks!

>> +
>> +function ff_vp9_copy32_neon, export=1
>> +        ldr             r12, [sp]
>> +        sub             r1,  r1,  #16
>> +        sub             r3,  r3,  #16
>> +1:
>> +        vld1.8          {q0},  [r2]!
>> +        vst1.8          {q0},  [r0, :128]!
>> +        subs            r12, r12, #1
>> +        vld1.8          {q1},  [r2], r3
>> +        vst1.8          {q1},  [r0, :128], r1
>> +        bne             1b
>> +        bx              lr
>> +endfunc
>> +
>> +function ff_vp9_avg32_neon, export=1
>> +        ldr             r12, [sp]
>> +        sub             r1,  r1,  #16
>> +        sub             r3,  r3,  #16
>> +1:
>> +        vld1.8          {q2},  [r2]!
>> +        vld1.8          {q0},  [r0, :128]!
>> +        vld1.8          {q3},  [r2], r3
>> +        vrhadd.u8       q0,  q0,  q2
>> +        vld1.8          {q1},  [r0, :128]
>> +        vrhadd.u8       q1,  q1,  q3
>> +        sub             r0,  r0,  #16
>
> 32-byte load for dst will leave r0 unmodified

Yep, immensely helpful!

>> +        vst1.8          {q0},  [r0, :128]!
>> +        vst1.8          {q1},  [r0, :128], r1
>> +        subs            r12, r12, #1
>> +        bne             1b
>> +        bx              lr
>> +endfunc
>> +
>> +function ff_vp9_copy16_neon, export=1
>> +        ldr             r12, [sp]
>> +        push            {r4-r5}
>> +        add             r4,  r0,  r1
>> +        add             r5,  r2,  r3
>> +        add             r1,  r1,  r1
>> +        add             r3,  r3,  r3
>> +1:
>> +        vld1.8          {q0},  [r2], r3
>> +        vld1.8          {q1},  [r5], r3
>> +        subs            r12, r12, #2
>> +        vst1.8          {q0},  [r0, :128], r1
>> +        vst1.8          {q1},  [r4, :128], r1
>> +        bne             1b
>> +        pop             {r4-r5}
>> +        bx              lr
>> +endfunc
>> +
>> +function ff_vp9_avg16_neon, export=1
>> +        ldr             r12, [sp]
>> +1:
>> +        vld1.8          {q2},  [r2], r3
>> +        vld1.8          {q0},  [r0, :128], r1
>> +        vld1.8          {q3},  [r2], r3
>> +        vrhadd.u8       q0,  q0,  q2
>> +        vld1.8          {q1},  [r0, :128]
>> +        sub             r0,  r0,  r1
>
> have you tried storing q0 with writeback and then loading q1?

I tried it now, but it gave a very minor speedup on two of the tested 
cores, and an equally large slowdown on the other ones, so it doesn't seem 
to be useful.

>> +        vrhadd.u8       q1,  q1,  q3
>> +        subs            r12, r12, #2
>> +        vst1.8          {q0},  [r0, :128], r1
>> +        vst1.8          {q1},  [r0, :128], r1
>> +        bne             1b
>> +        bx              lr
>> +endfunc
>> +
>> +function ff_vp9_copy8_neon, export=1
>> +        ldr             r12, [sp]
>> +1:
>> +        vld1.8          {d0},  [r2], r3
>> +        vld1.8          {d1},  [r2], r3
>> +        subs            r12, r12, #2
>> +        vst1.8          {d0},  [r0, :64], r1
>> +        vst1.8          {d1},  [r0, :64], r1
>> +        bne             1b
>> +        bx              lr
>> +endfunc
>> +
>> +function ff_vp9_avg8_neon, export=1
>> +        ldr             r12, [sp]
>> +1:
>> +        vld1.8          {d2},  [r2], r3
>> +        vld1.8          {d0},  [r0, :64], r1
>> +        vld1.8          {d3},  [r2], r3
>> +        vrhadd.u8       d0,  d0,  d2
>> +        vld1.8          {d1},  [r0, :64]
>> +        sub             r0,  r0,  r1
>
> same as 16 although it's probably silly for size 8, using an additional
> register would the other possibility to speed it up

Didn't turn out to help on more than 1 core actually, and gave an equal 
slowdown on the others

>> +.macro do_8tap_h_size size
>> +do_8tap_h put, \size, 3, 4
>> +do_8tap_h avg, \size, 3, 4
>> +do_8tap_h put, \size, 4, 3
>> +do_8tap_h avg, \size, 4, 3
>> +.endm
>> +
>> +do_8tap_h_size 4
>> +do_8tap_h_size 8
>> +do_8tap_h_size 16
>> +do_8tap_h_size 32
>
> I'm not sure if it's worth to have the size 32+ version. The additional
> loop checks are probably not noticeable in size 16 case and it would
> reduce the binary size.

Fair point. This reduced the code size for this object file from 13308 
bytes to 11724 bytes, which is kinda significant.

> The other idea for keeping the calculation in signed 16-bit would have
> been using a negative constant as offset since the range doesn't exceed
> 16-bit. Not faster in checkasm but smaller binary size.
>
> No need to try that. Current implementation is fine for me and looks
> quite nice.

Thanks!

>> +@ Evaluate the filter twice in parallel, from the inputs src1-src9
>> into dst1-dst2
>> +@ (src1-src8 into dst1, src2-src9 into dst2), adding idx2 separately
>> +@ at the end with saturation
>> +.macro convolve dst1, dst2, src1, src2, src3, src4, src5, src6, src7, src8, src9, idx1, idx2, tmp1, tmp2
>> +        vmul.s16        \dst1, \src1, d0[0]
>> +        vmul.s16        \dst2, \src2, d0[0]
>> +        vmla.s16        \dst1, \src2, d0[1]
>> +        vmla.s16        \dst2, \src3, d0[1]
>> +        vmla.s16        \dst1, \src3, d0[2]
>> +        vmla.s16        \dst2, \src4, d0[2]
>> +.if \idx1 == 3
>> +        vmla.s16        \dst1, \src4, d0[3]
>> +        vmla.s16        \dst2, \src5, d0[3]
>> +.else
>> +        vmla.s16        \dst1, \src5, d1[0]
>> +        vmla.s16        \dst2, \src6, d1[0]
>> +.endif
>> +        vmla.s16        \dst1, \src6, d1[1]
>> +        vmla.s16        \dst2, \src7, d1[1]
>> +        vmla.s16        \dst1, \src7, d1[2]
>> +        vmla.s16        \dst2, \src8, d1[2]
>> +        vmla.s16        \dst1, \src8, d1[3]
>> +        vmla.s16        \dst2, \src9, d1[3]
>> +.if \idx2 == 3
>> +        vmul.s16        \tmp1, \src4, d0[3]
>> +        vmul.s16        \tmp2, \src5, d0[3]
>> +.else
>> +        vmul.s16        \tmp1, \src5, d1[0]
>> +        vmul.s16        \tmp2, \src6, d1[0]
>> +.endif
>> +        vqadd.s16       \dst1, \dst1, \tmp1
>> +        vqadd.s16       \dst2, \dst2, \tmp2
>> +.endm
>
> the negative terms could be accumulated in tmp1/2 I doubt it makes a
> difference in practice but reduces data dependencies.

This did actually turn out to help quite a lot on A53 (from 11707 cycles 
to 9649, for the 64v function). Very marginal slowdowns on A8 and A9 
though, but clearly worthwhile doing.

> ...
>
>> +@ Instantiate a vertical filter function for filtering a 4 pixels
>> wide
>> +@ slice. The first half of the registers contain one row, while the second
>> +@ half of a register contains the second-next row (also stored in the first
>> +@ half of the register two steps ahead). The convolution does two outputs
>> +@ at a time; the output of q5-q12 into one, and q4-q13 into another one.
>> +@ The first half of first output is the first output row, the first half
>> +@ of the other output is the second output row. The second halves of the
>> +@ registers are rows 3 and 4.
>> +@ This only is designed to work for 4 or 8 output lines.
>> +.macro do_8tap_4v type, idx1, idx2
>> +function \type\()_8tap_4v_\idx1\idx2
>> +        sub             r2,  r2,  r3, lsl #1
>> +        sub             r2,  r2,  r3
>> +        vld1.16         {q0},  [r12, :128]
>> +
>> +        vld1.32         {d2[]},   [r2], r3
>> +        vld1.32         {d3[]},   [r2], r3
>> +        vld1.32         {d4[]},   [r2], r3
>> +        vld1.32         {d5[]},   [r2], r3
>> +        vld1.32         {d6[]},   [r2], r3
>> +        vld1.32         {d7[]},   [r2], r3
>> +        vld1.32         {d8[]},   [r2], r3
>> +        vld1.32         {d9[]},   [r2], r3
>> +        vld1.32         {d28[]},  [r2]
>> +        sub             r2,  r2,  r3, lsl #2
>> +        sub             r2,  r2,  r3, lsl #1
>> +        vld1.32         {d2[1]},  [r2], r3
>
> vext.8 d2,  d2,  d4,  #4 should be faster than loading. it works since
> we loaded data to all lanes

Oh, clever! This was also quite helpful, especially since this function is 
pretty short and fast anyway, so the change is quite noticeable.

>> +        vld1.32         {d3[1]},  [r2], r3
>> +        vmovl.u8        q5,  d2
>> +        vld1.32         {d4[1]},  [r2], r3
>> +        vmovl.u8        q6,  d3
>> +        vld1.32         {d5[1]},  [r2], r3
>> +        vmovl.u8        q7,  d4
>> +        vld1.32         {d6[1]},  [r2], r3
>> +        vmovl.u8        q8,  d5
>> +        vld1.32         {d7[1]},  [r2], r3
>> +        vmovl.u8        q9,  d6
>> +        vld1.32         {d8[1]},  [r2], r3
>> +        vmovl.u8        q10, d7
>> +        vld1.32         {d9[1]},  [r2], r3
>> +        vmovl.u8        q11, d8
>> +        vld1.32         {d28[1]}, [r2]
>> +        sub             r2,  r2,  r3
>> +
>> +        vmovl.u8        q12, d9
>> +        vmovl.u8        q13, d28
>> +
>> +        convolve        q1,  q2,  q5,  q6,  q7,  q8,  q9,  q10, q11, q12, q13, \idx1, \idx2, q4, q3
>> +        do_store4       q1,  d2,  q2,  d4,  d3,  d5,  \type
>> +        subs            r4,  r4,  #4
>> +        beq             9f
>> +
>> +        vld1.32         {d2[]},   [r2], r3
>> +        vld1.32         {d3[]},   [r2], r3
>> +        vld1.32         {d4[]},   [r2], r3
>> +        vld1.32         {d5[]},   [r2], r3
>> +        sub             r2,  r2,  r3, lsl #1
>> +        vld1.32         {d2[1]},  [r2], r3
>> +        vld1.32         {d3[1]},  [r2], r3
>> +        vmovl.u8        q14, d2
>> +        vld1.32         {d4[1]},  [r2], r3
>> +        vmovl.u8        q15, d3
>> +        vld1.32         {d5[1]},  [r2], r3
>> +        vmovl.u8        q5,  d4
>> +        vmovl.u8        q6,  d5
>> +
>> +        convolve        q1,  q2,  q9,  q10, q11, q12, q13, q14, q15, q5,  q6,  \idx1, \idx2, q4, q3
>> +        do_store4       q1,  d2,  q2,  d4,  d3,  d5,  \type
>> +
>> +9:
>> +        vpop            {q4-q7}
>> +        pop             {r4-r5}
>> +        bx              lr
>> +endfunc
>> +.endm
>> +
>> +do_8tap_4v put, 3, 4
>> +do_8tap_4v put, 4, 3
>> +do_8tap_4v avg, 3, 4
>> +do_8tap_4v avg, 4, 3
>> +
>> +.macro do_8tap_v_func type, filter, size
>> +function ff_vp9_\type\()_\filter\()\size\()_v_neon, export=1
>> +        push            {r4-r5}
>> +        vpush           {q4-q7}
>> +        ldr             r4,  [sp, #72]
>> +        ldr             r5,  [sp, #80]
>> +        movrel          r12, \filter\()_filter-16
>> +        add             r12,  r12, r5, lsl #4
>> +        cmp             r5,  #8
>> +        mov             r5,  #\size
>
> a little confusing that this changes r5 and r12 compared to the
> horizontal mc, changing the horizontal mc so that r5 holds the width
> and r12 the filter constants/tmp reg would work if you care

Indeed; I changed that and now it's consistent.

Thanks for the review! I'll post the updated patch, and apply the same 
review comments to the aarch64 version and repost that one as soon as I 
get them applied there.

// Martin
Janne Grunau Nov. 2, 2016, 6:42 p.m. | #3
On 2016-11-02 13:11:19 +0200, Martin Storsjö wrote:
> On Wed, 2 Nov 2016, Janne Grunau wrote:
> 
> >On 2016-10-19 22:18:43 +0300, Martin Storsjö wrote:
> 
> >>+    /* We only need h + 7 lines, but the horizontal filter assumes an             \
> >>+     * even number of rows, so filter h + 8 lines here. */                        \
> >>+    ff_vp9_put_##filter##sz##_h_neon(temp, 64,                                    \
> >>+                                     src - 3 * src_stride, src_stride,            \
> >>+                                     h + 8, mx, 0);                               \
> >>+    ff_vp9_##op##_##filter##sz##_v_neon(dst, dst_stride,                          \
> >>+                                        temp + 3 * 64, 64,                        \
> >>+                                        h, 0, my);                                \
> >
> >I guess you haven't tried implementing the diagonal mc fully in asm?
> >Probably not worth the effort since the only significant gain comes from
> >keeping the temporary values in registers which works on size 4 and 8 and
> >maybe 16 for aarch64 wich are probably not that important.
> 
> I didn't try that fully, no. I did try an asm frontend just like this one,
> though, to avoid a separate vpush/vpop in each of them, and while it does
> save a little, I had to restructure the end of the filter function, which
> cost a little for the plain-horizontal/vertical functions. All in all I
> guess it would be a gain, but not really worth it I think. Being able to
> keep all the intermediates in registers would probably make it more
> worthwhile, but that would also be even more effort. Since you need 7 more
> rows than the actual input size, and the height can be width*2, I think it
> would be hard to keep the intermediates for anything more than size 4 in
> registers even if you'd do a handmade version for it.

Yes, the variable height complicates it further, I guess 8 and 16 (on 
aarch64) works only if you merge the horizontal and vertical filter 
completely. I don't think it is worth the effort and patch good as it is 
anyway.

> >>+        vrhadd.u8       q3,  q3,  q11
> >>+        vst1.8          {q0},  [r0, :128]!
> >>+        vst1.8          {q1},  [r0, :128]!
> >>+        vst1.8          {q2},  [r0, :128]!
> >>+        vst1.8          {q3},  [r0, :128], r1
> >>+        subs            r12, r12, #1
> >>+        bne             1b
> >>+        bx              lr
> >>+endfunc
> >
> >Have you tried 4 d-register loads/stores? If it's not slower it's
> >preferable since it uses less instructions. Same for size 32 with the
> >additional advantange of not having to adjust the stride
> 
> Oh, why didn't I remember those instructions? Yes, this gives a huge gain,
> like a 20% speedup in the 32/64 functions. Thanks!

More than expected and I almost didn't ask for it since I assumed you 
had tried.

> >>+@ Evaluate the filter twice in parallel, from the inputs src1-src9
> >>into dst1-dst2
> >>+@ (src1-src8 into dst1, src2-src9 into dst2), adding idx2 separately
> >>+@ at the end with saturation
> >>+.macro convolve dst1, dst2, src1, src2, src3, src4, src5, src6, src7, src8, src9, idx1, idx2, tmp1, tmp2
> >>+        vmul.s16        \dst1, \src1, d0[0]
> >>+        vmul.s16        \dst2, \src2, d0[0]
> >>+        vmla.s16        \dst1, \src2, d0[1]
> >>+        vmla.s16        \dst2, \src3, d0[1]
> >>+        vmla.s16        \dst1, \src3, d0[2]
> >>+        vmla.s16        \dst2, \src4, d0[2]
> >>+.if \idx1 == 3
> >>+        vmla.s16        \dst1, \src4, d0[3]
> >>+        vmla.s16        \dst2, \src5, d0[3]
> >>+.else
> >>+        vmla.s16        \dst1, \src5, d1[0]
> >>+        vmla.s16        \dst2, \src6, d1[0]
> >>+.endif
> >>+        vmla.s16        \dst1, \src6, d1[1]
> >>+        vmla.s16        \dst2, \src7, d1[1]
> >>+        vmla.s16        \dst1, \src7, d1[2]
> >>+        vmla.s16        \dst2, \src8, d1[2]
> >>+        vmla.s16        \dst1, \src8, d1[3]
> >>+        vmla.s16        \dst2, \src9, d1[3]
> >>+.if \idx2 == 3
> >>+        vmul.s16        \tmp1, \src4, d0[3]
> >>+        vmul.s16        \tmp2, \src5, d0[3]
> >>+.else
> >>+        vmul.s16        \tmp1, \src5, d1[0]
> >>+        vmul.s16        \tmp2, \src6, d1[0]
> >>+.endif
> >>+        vqadd.s16       \dst1, \dst1, \tmp1
> >>+        vqadd.s16       \dst2, \dst2, \tmp2
> >>+.endm
> >
> >the negative terms could be accumulated in tmp1/2 I doubt it makes a
> >difference in practice but reduces data dependencies.
> 
> This did actually turn out to help quite a lot on A53 (from 11707 cycles to
> 9649, for the 64v function). Very marginal slowdowns on A8 and A9 though,
> but clearly worthwhile doing.

A little surprising. Either vmla is really slow on the cortex-a53 or its 
neon unit is contrary to reports in tech press at least partially 
128-bit wide.

Janne

Patch

diff --git a/libavcodec/arm/Makefile b/libavcodec/arm/Makefile
index bd4dd4e..2638230 100644
--- a/libavcodec/arm/Makefile
+++ b/libavcodec/arm/Makefile
@@ -45,6 +45,7 @@  OBJS-$(CONFIG_MLP_DECODER)             += arm/mlpdsp_init_arm.o
 OBJS-$(CONFIG_RV40_DECODER)            += arm/rv40dsp_init_arm.o
 OBJS-$(CONFIG_VORBIS_DECODER)          += arm/vorbisdsp_init_arm.o
 OBJS-$(CONFIG_VP6_DECODER)             += arm/vp6dsp_init_arm.o
+OBJS-$(CONFIG_VP9_DECODER)             += arm/vp9dsp_init_arm.o
 
 
 # ARMv5 optimizations
@@ -138,3 +139,4 @@  NEON-OBJS-$(CONFIG_RV40_DECODER)       += arm/rv34dsp_neon.o            \
                                           arm/rv40dsp_neon.o
 NEON-OBJS-$(CONFIG_VORBIS_DECODER)     += arm/vorbisdsp_neon.o
 NEON-OBJS-$(CONFIG_VP6_DECODER)        += arm/vp6dsp_neon.o
+NEON-OBJS-$(CONFIG_VP9_DECODER)        += arm/vp9mc_neon.o
diff --git a/libavcodec/arm/vp9dsp_init_arm.c b/libavcodec/arm/vp9dsp_init_arm.c
new file mode 100644
index 0000000..db8c683
--- /dev/null
+++ b/libavcodec/arm/vp9dsp_init_arm.c
@@ -0,0 +1,140 @@ 
+/*
+ * Copyright (c) 2016 Google Inc.
+ *
+ * This file is part of Libav.
+ *
+ * Libav is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * Libav is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with Libav; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <stdint.h>
+
+#include "libavutil/attributes.h"
+#include "libavutil/arm/cpu.h"
+#include "libavcodec/vp9.h"
+
+#define declare_fpel(type, sz)                                          \
+void ff_vp9_##type##sz##_neon(uint8_t *dst, ptrdiff_t dst_stride,       \
+                              const uint8_t *src, ptrdiff_t src_stride, \
+                              int h, int mx, int my)
+
+#define declare_copy_avg(sz) \
+    declare_fpel(copy, sz);  \
+    declare_fpel(avg , sz)
+
+#define decl_mc_func(op, filter, dir, sz)                                                \
+void ff_vp9_##op##_##filter##sz##_##dir##_neon(uint8_t *dst, ptrdiff_t dst_stride,       \
+                                               const uint8_t *src, ptrdiff_t src_stride, \
+                                               int h, int mx, int my)
+
+#define define_8tap_2d_fn(op, filter, sz)                                         \
+static void op##_##filter##sz##_hv_neon(uint8_t *dst, ptrdiff_t dst_stride,       \
+                                        const uint8_t *src, ptrdiff_t src_stride, \
+                                        int h, int mx, int my)                    \
+{                                                                                 \
+    LOCAL_ALIGNED_16(uint8_t, temp, [72 * 64]);                                   \
+    /* We only need h + 7 lines, but the horizontal filter assumes an             \
+     * even number of rows, so filter h + 8 lines here. */                        \
+    ff_vp9_put_##filter##sz##_h_neon(temp, 64,                                    \
+                                     src - 3 * src_stride, src_stride,            \
+                                     h + 8, mx, 0);                               \
+    ff_vp9_##op##_##filter##sz##_v_neon(dst, dst_stride,                          \
+                                        temp + 3 * 64, 64,                        \
+                                        h, 0, my);                                \
+}
+
+#define decl_filter_funcs(op, dir, sz)  \
+    decl_mc_func(op, regular, dir, sz); \
+    decl_mc_func(op, sharp,   dir, sz); \
+    decl_mc_func(op, smooth,  dir, sz)
+
+#define decl_mc_funcs(sz)           \
+    decl_filter_funcs(put, h,  sz); \
+    decl_filter_funcs(avg, h,  sz); \
+    decl_filter_funcs(put, v,  sz); \
+    decl_filter_funcs(avg, v,  sz); \
+    decl_filter_funcs(put, hv, sz); \
+    decl_filter_funcs(avg, hv, sz)
+
+declare_copy_avg(64);
+declare_copy_avg(32);
+declare_copy_avg(16);
+declare_copy_avg(8);
+declare_copy_avg(4);
+
+decl_mc_funcs(64);
+decl_mc_funcs(32);
+decl_mc_funcs(16);
+decl_mc_funcs(8);
+decl_mc_funcs(4);
+
+#define define_8tap_2d_funcs(sz)        \
+    define_8tap_2d_fn(put, regular, sz) \
+    define_8tap_2d_fn(put, sharp,   sz) \
+    define_8tap_2d_fn(put, smooth,  sz) \
+    define_8tap_2d_fn(avg, regular, sz) \
+    define_8tap_2d_fn(avg, sharp,   sz) \
+    define_8tap_2d_fn(avg, smooth,  sz)
+
+define_8tap_2d_funcs(64)
+define_8tap_2d_funcs(32)
+define_8tap_2d_funcs(16)
+define_8tap_2d_funcs(8)
+define_8tap_2d_funcs(4)
+
+
+av_cold void ff_vp9dsp_init_arm(VP9DSPContext *dsp)
+{
+    int cpu_flags = av_get_cpu_flags();
+
+    if (have_neon(cpu_flags)) {
+#define init_fpel(idx1, idx2, sz, type)              \
+    dsp->mc[idx1][FILTER_8TAP_SMOOTH ][idx2][0][0] = \
+    dsp->mc[idx1][FILTER_8TAP_REGULAR][idx2][0][0] = \
+    dsp->mc[idx1][FILTER_8TAP_SHARP  ][idx2][0][0] = \
+    dsp->mc[idx1][FILTER_BILINEAR    ][idx2][0][0] = ff_vp9_##type##sz##_neon
+
+#define init_copy_avg(idx, sz)   \
+    init_fpel(idx, 0, sz, copy); \
+    init_fpel(idx, 1, sz, avg)
+
+#define init_mc_func(idx1, idx2, op, filter, fname, dir, mx, my, sz, pfx) \
+    dsp->mc[idx1][filter][idx2][mx][my] = pfx##op##_##fname##sz##_##dir##_neon
+
+#define init_mc_funcs(idx, dir, mx, my, sz, pfx)                                   \
+    init_mc_func(idx, 0, put, FILTER_8TAP_REGULAR, regular, dir, mx, my, sz, pfx); \
+    init_mc_func(idx, 0, put, FILTER_8TAP_SHARP,   sharp,   dir, mx, my, sz, pfx); \
+    init_mc_func(idx, 0, put, FILTER_8TAP_SMOOTH,  smooth,  dir, mx, my, sz, pfx); \
+    init_mc_func(idx, 1, avg, FILTER_8TAP_REGULAR, regular, dir, mx, my, sz, pfx); \
+    init_mc_func(idx, 1, avg, FILTER_8TAP_SHARP,   sharp,   dir, mx, my, sz, pfx); \
+    init_mc_func(idx, 1, avg, FILTER_8TAP_SMOOTH,  smooth,  dir, mx, my, sz, pfx)
+
+#define init_mc_funcs_dirs(idx, sz)            \
+    init_mc_funcs(idx, h,  1, 0, sz, ff_vp9_); \
+    init_mc_funcs(idx, v,  0, 1, sz, ff_vp9_); \
+    init_mc_funcs(idx, hv, 1, 1, sz,)
+
+        init_copy_avg(0, 64);
+        init_copy_avg(1, 32);
+        init_copy_avg(2, 16);
+        init_copy_avg(3, 8);
+        init_copy_avg(4, 4);
+
+        init_mc_funcs_dirs(0, 64);
+        init_mc_funcs_dirs(1, 32);
+        init_mc_funcs_dirs(2, 16);
+        init_mc_funcs_dirs(3, 8);
+        init_mc_funcs_dirs(4, 4);
+    }
+}
diff --git a/libavcodec/arm/vp9mc_neon.S b/libavcodec/arm/vp9mc_neon.S
new file mode 100644
index 0000000..754ac50
--- /dev/null
+++ b/libavcodec/arm/vp9mc_neon.S
@@ -0,0 +1,787 @@ 
+/*
+ * Copyright (c) 2016 Google Inc.
+ *
+ * This file is part of Libav.
+ *
+ * Libav is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * Libav is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with Libav; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include "libavutil/arm/asm.S"
+
+const regular_filter, align=4
+        .short  0,  1,  -5, 126,   8,  -3,  1,  0
+        .short -1,  3, -10, 122,  18,  -6,  2,  0
+        .short -1,  4, -13, 118,  27,  -9,  3, -1
+        .short -1,  4, -16, 112,  37, -11,  4, -1
+        .short -1,  5, -18, 105,  48, -14,  4, -1
+        .short -1,  5, -19,  97,  58, -16,  5, -1
+        .short -1,  6, -19,  88,  68, -18,  5, -1
+        .short -1,  6, -19,  78,  78, -19,  6, -1
+        .short -1,  5, -18,  68,  88, -19,  6, -1
+        .short -1,  5, -16,  58,  97, -19,  5, -1
+        .short -1,  4, -14,  48, 105, -18,  5, -1
+        .short -1,  4, -11,  37, 112, -16,  4, -1
+        .short -1,  3,  -9,  27, 118, -13,  4, -1
+        .short  0,  2,  -6,  18, 122, -10,  3, -1
+        .short  0,  1,  -3,   8, 126,  -5,  1,  0
+endconst
+
+const sharp_filter, align=4
+        .short -1,  3,  -7, 127,   8,  -3,  1,  0
+        .short -2,  5, -13, 125,  17,  -6,  3, -1
+        .short -3,  7, -17, 121,  27, -10,  5, -2
+        .short -4,  9, -20, 115,  37, -13,  6, -2
+        .short -4, 10, -23, 108,  48, -16,  8, -3
+        .short -4, 10, -24, 100,  59, -19,  9, -3
+        .short -4, 11, -24,  90,  70, -21, 10, -4
+        .short -4, 11, -23,  80,  80, -23, 11, -4
+        .short -4, 10, -21,  70,  90, -24, 11, -4
+        .short -3,  9, -19,  59, 100, -24, 10, -4
+        .short -3,  8, -16,  48, 108, -23, 10, -4
+        .short -2,  6, -13,  37, 115, -20,  9, -4
+        .short -2,  5, -10,  27, 121, -17,  7, -3
+        .short -1,  3,  -6,  17, 125, -13,  5, -2
+        .short  0,  1,  -3,   8, 127,  -7,  3, -1
+endconst
+
+const smooth_filter, align=4
+        .short -3, -1,  32,  64,  38,   1, -3,  0
+        .short -2, -2,  29,  63,  41,   2, -3,  0
+        .short -2, -2,  26,  63,  43,   4, -4,  0
+        .short -2, -3,  24,  62,  46,   5, -4,  0
+        .short -2, -3,  21,  60,  49,   7, -4,  0
+        .short -1, -4,  18,  59,  51,   9, -4,  0
+        .short -1, -4,  16,  57,  53,  12, -4, -1
+        .short -1, -4,  14,  55,  55,  14, -4, -1
+        .short -1, -4,  12,  53,  57,  16, -4, -1
+        .short  0, -4,   9,  51,  59,  18, -4, -1
+        .short  0, -4,   7,  49,  60,  21, -3, -2
+        .short  0, -4,   5,  46,  62,  24, -3, -2
+        .short  0, -4,   4,  43,  63,  26, -2, -2
+        .short  0, -3,   2,  41,  63,  29, -2, -2
+        .short  0, -3,   1,  38,  64,  32, -1, -3
+endconst
+
+@ All public functions in this file have the following signature:
+@ typedef void (*vp9_mc_func)(uint8_t *dst, ptrdiff_t dst_stride,
+@                            const uint8_t *ref, ptrdiff_t ref_stride,
+@                            int h, int mx, int my);
+
+function ff_vp9_copy64_neon, export=1
+        ldr             r12, [sp]
+        sub             r1,  r1,  #48
+        sub             r3,  r3,  #48
+1:
+        vld1.8          {q0},  [r2]!
+        vld1.8          {q1},  [r2]!
+        vst1.8          {q0},  [r0, :128]!
+        vld1.8          {q2},  [r2]!
+        vst1.8          {q1},  [r0, :128]!
+        vld1.8          {q3},  [r2], r3
+        vst1.8          {q2},  [r0, :128]!
+        subs            r12, r12, #1
+        vst1.8          {q3},  [r0, :128], r1
+        bne             1b
+        bx              lr
+endfunc
+
+function ff_vp9_avg64_neon, export=1
+        ldr             r12, [sp]
+        sub             r1,  r1,  #48
+        sub             r3,  r3,  #48
+1:
+        vld1.8          {q8},  [r2]!
+        vld1.8          {q0},  [r0, :128]!
+        vld1.8          {q9},  [r2]!
+        vld1.8          {q1},  [r0, :128]!
+        vrhadd.u8       q0,  q0,  q8
+        vld1.8          {q10}, [r2]!
+        vld1.8          {q2},  [r0, :128]!
+        vrhadd.u8       q1,  q1,  q9
+        vld1.8          {q11}, [r2], r3
+        vld1.8          {q3},  [r0, :128]
+        vrhadd.u8       q2,  q2,  q10
+        sub             r0,  r0,  #48
+        vrhadd.u8       q3,  q3,  q11
+        vst1.8          {q0},  [r0, :128]!
+        vst1.8          {q1},  [r0, :128]!
+        vst1.8          {q2},  [r0, :128]!
+        vst1.8          {q3},  [r0, :128], r1
+        subs            r12, r12, #1
+        bne             1b
+        bx              lr
+endfunc
+
+function ff_vp9_copy32_neon, export=1
+        ldr             r12, [sp]
+        sub             r1,  r1,  #16
+        sub             r3,  r3,  #16
+1:
+        vld1.8          {q0},  [r2]!
+        vst1.8          {q0},  [r0, :128]!
+        subs            r12, r12, #1
+        vld1.8          {q1},  [r2], r3
+        vst1.8          {q1},  [r0, :128], r1
+        bne             1b
+        bx              lr
+endfunc
+
+function ff_vp9_avg32_neon, export=1
+        ldr             r12, [sp]
+        sub             r1,  r1,  #16
+        sub             r3,  r3,  #16
+1:
+        vld1.8          {q2},  [r2]!
+        vld1.8          {q0},  [r0, :128]!
+        vld1.8          {q3},  [r2], r3
+        vrhadd.u8       q0,  q0,  q2
+        vld1.8          {q1},  [r0, :128]
+        vrhadd.u8       q1,  q1,  q3
+        sub             r0,  r0,  #16
+        vst1.8          {q0},  [r0, :128]!
+        vst1.8          {q1},  [r0, :128], r1
+        subs            r12, r12, #1
+        bne             1b
+        bx              lr
+endfunc
+
+function ff_vp9_copy16_neon, export=1
+        ldr             r12, [sp]
+        push            {r4-r5}
+        add             r4,  r0,  r1
+        add             r5,  r2,  r3
+        add             r1,  r1,  r1
+        add             r3,  r3,  r3
+1:
+        vld1.8          {q0},  [r2], r3
+        vld1.8          {q1},  [r5], r3
+        subs            r12, r12, #2
+        vst1.8          {q0},  [r0, :128], r1
+        vst1.8          {q1},  [r4, :128], r1
+        bne             1b
+        pop             {r4-r5}
+        bx              lr
+endfunc
+
+function ff_vp9_avg16_neon, export=1
+        ldr             r12, [sp]
+1:
+        vld1.8          {q2},  [r2], r3
+        vld1.8          {q0},  [r0, :128], r1
+        vld1.8          {q3},  [r2], r3
+        vrhadd.u8       q0,  q0,  q2
+        vld1.8          {q1},  [r0, :128]
+        sub             r0,  r0,  r1
+        vrhadd.u8       q1,  q1,  q3
+        subs            r12, r12, #2
+        vst1.8          {q0},  [r0, :128], r1
+        vst1.8          {q1},  [r0, :128], r1
+        bne             1b
+        bx              lr
+endfunc
+
+function ff_vp9_copy8_neon, export=1
+        ldr             r12, [sp]
+1:
+        vld1.8          {d0},  [r2], r3
+        vld1.8          {d1},  [r2], r3
+        subs            r12, r12, #2
+        vst1.8          {d0},  [r0, :64], r1
+        vst1.8          {d1},  [r0, :64], r1
+        bne             1b
+        bx              lr
+endfunc
+
+function ff_vp9_avg8_neon, export=1
+        ldr             r12, [sp]
+1:
+        vld1.8          {d2},  [r2], r3
+        vld1.8          {d0},  [r0, :64], r1
+        vld1.8          {d3},  [r2], r3
+        vrhadd.u8       d0,  d0,  d2
+        vld1.8          {d1},  [r0, :64]
+        sub             r0,  r0,  r1
+        vrhadd.u8       d1,  d1,  d3
+        subs            r12, r12, #2
+        vst1.8          {d0},  [r0, :64], r1
+        vst1.8          {d1},  [r0, :64], r1
+        bne             1b
+        bx              lr
+endfunc
+
+function ff_vp9_copy4_neon, export=1
+        ldr             r12, [sp]
+1:
+        vld1.32         {d0[]},   [r2], r3
+        vld1.32         {d1[]},   [r2], r3
+        vst1.32         {d0[0]},  [r0, :32], r1
+        vld1.32         {d2[]},   [r2], r3
+        vst1.32         {d1[0]},  [r0, :32], r1
+        vld1.32         {d3[]},   [r2], r3
+        subs            r12, r12, #4
+        vst1.32         {d2[0]},  [r0, :32], r1
+        vst1.32         {d3[0]},  [r0, :32], r1
+        bne             1b
+        bx              lr
+endfunc
+
+function ff_vp9_avg4_neon, export=1
+        ldr             r12, [sp]
+1:
+        vld1.32         {d4[]},   [r2], r3
+        vld1.32         {d0[]},   [r0, :32], r1
+        vld1.32         {d5[]},   [r2], r3
+        vrhadd.u8       d0,  d0,  d4
+        vld1.32         {d1[]},   [r0, :32], r1
+        vld1.32         {d6[]},   [r2], r3
+        vrhadd.u8       d1,  d1,  d5
+        vld1.32         {d2[]},   [r0, :32], r1
+        vld1.32         {d7[]},   [r2], r3
+        vrhadd.u8       d2,  d2,  d6
+        vld1.32         {d3[]},   [r0, :32], r1
+        sub             r0,  r0,  r1, lsl #2
+        subs            r12, r12, #4
+        vst1.32         {d0[0]},  [r0, :32], r1
+        vrhadd.u8       d3,  d3,  d7
+        vst1.32         {d1[0]},  [r0, :32], r1
+        vst1.32         {d2[0]},  [r0, :32], r1
+        vst1.32         {d3[0]},  [r0, :32], r1
+        bne             1b
+        bx              lr
+endfunc
+
+@ Helper macros for vmul/vmla with a constant from either d0 or d1 depending on index
+.macro vmul_lane dst, src, idx
+.if \idx < 4
+       vmul.s16         \dst, \src, d0[\idx]
+.else
+       vmul.s16         \dst, \src, d1[\idx - 4]
+.endif
+.endm
+.macro vmla_lane dst, src, idx
+.if \idx < 4
+       vmla.s16         \dst, \src, d0[\idx]
+.else
+       vmla.s16         \dst, \src, d1[\idx - 4]
+.endif
+.endm
+
+@ Extract a vector from src1-src2 and src4-src5 (src1-src3 and src4-src6
+@ for size >= 16), and multiply-accumulate into dst1 and dst3 (or
+@ dst1-dst2 and dst3-dst4 for size >= 16)
+.macro extmla dst1, dst2, dst3, dst4, src1, src2, src3, src4, src5, src6, offset, size
+        vext.8          q14, \src1, \src2, #(2*\offset)
+        vext.8          q15, \src4, \src5, #(2*\offset)
+.if \size >= 16
+        vmla_lane       \dst1,  q14, \offset
+        vext.8          q5,  \src2, \src3, #(2*\offset)
+        vmla_lane       \dst3,  q15, \offset
+        vext.8          q6,  \src5, \src6, #(2*\offset)
+        vmla_lane       \dst2,  q5,  \offset
+        vmla_lane       \dst4,  q6,  \offset
+.else
+        vmla_lane       \dst1,  q14, \offset
+        vmla_lane       \dst3,  q15, \offset
+.endif
+.endm
+@ The same as above, but don't accumulate straight into the
+@ destination, but use a temp register and accumulate with saturation.
+.macro extmulqadd dst1, dst2, dst3, dst4, src1, src2, src3, src4, src5, src6, offset, size
+        vext.8          q14, \src1, \src2, #(2*\offset)
+        vext.8          q15, \src4, \src5, #(2*\offset)
+.if \size >= 16
+        vmul_lane       q14, q14, \offset
+        vext.8          q5,  \src2, \src3, #(2*\offset)
+        vmul_lane       q15, q15, \offset
+        vext.8          q6,  \src5, \src6, #(2*\offset)
+        vmul_lane       q5,  q5,  \offset
+        vmul_lane       q6,  q6,  \offset
+.else
+        vmul_lane       q14, q14, \offset
+        vmul_lane       q15, q15, \offset
+.endif
+        vqadd.s16       \dst1,  \dst1,  q14
+        vqadd.s16       \dst3,  \dst3,  q15
+.if \size >= 16
+        vqadd.s16       \dst2,  \dst2,  q5
+        vqadd.s16       \dst4,  \dst4,  q6
+.endif
+.endm
+
+
+@ Instantiate a horizontal filter function for the given size.
+@ This can work on 4, 8 or 16 pixels in parallel; for larger
+@ widths it will do 16 pixels at a time and loop horizontally.
+@ The actual width is passed in r12, and the height in r4.
+@ idx2 is the index of the largest filter coefficient (3 or 4)
+@ and idx1 is the other one of them.
+.macro do_8tap_h type, size, idx1, idx2
+function \type\()_8tap_\size\()h_\idx1\idx2
+        sub             r2,  r2,  #3
+        add             r6,  r0,  r1
+        add             r7,  r2,  r3
+        add             r1,  r1,  r1
+        add             r3,  r3,  r3
+        @ Only size > 16 loops horizontally and needs
+        @ reduced dst stride
+.if \size > 16
+        sub             r1,  r1,  r12
+.endif
+        @ size >= 16 loads two qwords and increments r2,
+        @ for size 4/8 it's enough with one qword and no
+        @ postincrement
+.if \size >= 16
+        sub             r3,  r3,  r12
+        sub             r3,  r3,  #8
+.endif
+        @ Load the filter vector
+        vld1.16         {q0},  [r5,:128]
+1:
+.if \size > 16
+        mov             r5,  r12
+.endif
+        @ Load src
+.if \size >= 16
+        vld1.8          {q8},  [r2]!
+        vld1.8          {q11}, [r7]!
+        vld1.8          {d20}, [r2]!
+        vld1.8          {d26}, [r7]!
+.else
+        vld1.8          {q8},  [r2]
+        vld1.8          {q11}, [r7]
+.endif
+        vmovl.u8        q9,  d17
+        vmovl.u8        q8,  d16
+        vmovl.u8        q12, d23
+        vmovl.u8        q11, d22
+.if \size >= 16
+        vmovl.u8        q10, d20
+        vmovl.u8        q13, d26
+.endif
+2:
+
+        @ Accumulate, adding idx2 last with a separate
+        @ saturating add. The positive filter coefficients
+        @ for all indices except idx2 must add up to less
+        @ than 127 for this not to overflow.
+        vmul.s16        q1,  q8,  d0[0]
+        vmul.s16        q3,  q11, d0[0]
+.if \size >= 16
+        vmul.s16        q2,  q9,  d0[0]
+        vmul.s16        q4,  q12, d0[0]
+.endif
+        extmla          q1,  q2,  q3,  q4,  q8,  q9,  q10,  q11, q12, q13, 1,     \size
+        extmla          q1,  q2,  q3,  q4,  q8,  q9,  q10,  q11, q12, q13, 2,     \size
+        extmla          q1,  q2,  q3,  q4,  q8,  q9,  q10,  q11, q12, q13, \idx1, \size
+        extmla          q1,  q2,  q3,  q4,  q8,  q9,  q10,  q11, q12, q13, 5,     \size
+        extmla          q1,  q2,  q3,  q4,  q8,  q9,  q10,  q11, q12, q13, 6,     \size
+        extmla          q1,  q2,  q3,  q4,  q8,  q9,  q10,  q11, q12, q13, 7,     \size
+        extmulqadd      q1,  q2,  q3,  q4,  q8,  q9,  q10,  q11, q12, q13, \idx2, \size
+
+        @ Round, shift and saturate
+        vqrshrun.s16    d2,  q1,  #7
+        vqrshrun.s16    d6,  q3,  #7
+.if \size >= 16
+        vqrshrun.s16    d3,  q2,  #7
+        vqrshrun.s16    d7,  q4,  #7
+.endif
+        @ Average
+.ifc \type,avg
+.if \size >= 16
+        vld1.8          {q14}, [r0,:128]
+        vld1.8          {q15}, [r6,:128]
+        vrhadd.u8       q1,  q1,  q14
+        vrhadd.u8       q3,  q3,  q15
+.elseif \size == 8
+        vld1.8          {d28}, [r0,:64]
+        vld1.8          {d30}, [r6,:64]
+        vrhadd.u8       d2,  d2,  d28
+        vrhadd.u8       d6,  d6,  d30
+.else
+        @ We only need d28[0], but [] is faster on some cores
+        vld1.32         {d28[]}, [r0,:32]
+        vld1.32         {d30[]}, [r6,:32]
+        vrhadd.u8       d2,  d2,  d28
+        vrhadd.u8       d6,  d6,  d30
+.endif
+.endif
+        @ Store and loop horizontally (for size > 16)
+.if \size > 16
+        vst1.8          {q1}, [r0,:128]!
+        vst1.8          {q3}, [r6,:128]!
+        vmov            q8,  q10
+        vmov            q11, q13
+        subs            r5,  r5,  #16
+        beq             3f
+        vld1.8          {q10}, [r2]!
+        vld1.8          {q13}, [r7]!
+        vmovl.u8        q9,  d20
+        vmovl.u8        q10, d21
+        vmovl.u8        q12, d26
+        vmovl.u8        q13, d27
+        b               2b
+.elseif \size == 16
+        vst1.8          {q1}, [r0,:128]
+        vst1.8          {q3}, [r6,:128]
+.elseif \size == 8
+        vst1.8          {d2}, [r0,:64]
+        vst1.8          {d6}, [r6,:64]
+.else @ \size == 4
+        vst1.32         {d2[0]}, [r0,:32]
+        vst1.32         {d6[0]}, [r6,:32]
+.endif
+3:
+        @ Loop vertically
+        add             r0,  r0,  r1
+        add             r6,  r6,  r1
+        add             r2,  r2,  r3
+        add             r7,  r7,  r3
+        subs            r4,  r4,  #2
+        bne             1b
+.if \size >= 16
+        vpop            {q4-q6}
+.endif
+        pop             {r4-r7}
+        bx              lr
+endfunc
+.endm
+
+.macro do_8tap_h_size size
+do_8tap_h put, \size, 3, 4
+do_8tap_h avg, \size, 3, 4
+do_8tap_h put, \size, 4, 3
+do_8tap_h avg, \size, 4, 3
+.endm
+
+do_8tap_h_size 4
+do_8tap_h_size 8
+do_8tap_h_size 16
+do_8tap_h_size 32
+
+.macro do_8tap_h_func type, filter, size
+function ff_vp9_\type\()_\filter\()\size\()_h_neon, export=1
+        push            {r4-r7}
+.if \size >= 16
+        vpush           {q4-q6}
+        ldr             r4,  [sp, #64]
+        ldr             r5,  [sp, #68]
+.else
+        ldr             r4,  [sp, #16]
+        ldr             r5,  [sp, #20]
+.endif
+        movrel          r12, \filter\()_filter-16
+        cmp             r5,  #8
+        add             r5,  r12, r5, lsl #4
+        mov             r12, #\size
+.if \size > 16
+        bge             \type\()_8tap_32h_34
+        b               \type\()_8tap_32h_43
+.else
+        bge             \type\()_8tap_\size\()h_34
+        b               \type\()_8tap_\size\()h_43
+.endif
+endfunc
+.endm
+
+.macro do_8tap_h_filters size
+do_8tap_h_func put, regular, \size
+do_8tap_h_func avg, regular, \size
+do_8tap_h_func put, sharp,   \size
+do_8tap_h_func avg, sharp,   \size
+do_8tap_h_func put, smooth,  \size
+do_8tap_h_func avg, smooth,  \size
+.endm
+
+do_8tap_h_filters 64
+do_8tap_h_filters 32
+do_8tap_h_filters 16
+do_8tap_h_filters 8
+do_8tap_h_filters 4
+
+
+@ Vertical filters
+
+@ Round, shift and saturate and store qreg1-2 over 4 lines
+.macro do_store4 qreg1, dreg1, qreg2, dreg2, tmp1, tmp2, type
+        vqrshrun.s16    \dreg1,  \qreg1, #7
+        vqrshrun.s16    \dreg2,  \qreg2, #7
+.ifc \type,avg
+        vld1.32         {\tmp1[]},   [r0,:32], r1
+        vld1.32         {\tmp2[]},   [r0,:32], r1
+        vld1.32         {\tmp1[1]},  [r0,:32], r1
+        vld1.32         {\tmp2[1]},  [r0,:32], r1
+        vrhadd.u8       \dreg1,  \dreg1,  \tmp1
+        vrhadd.u8       \dreg2,  \dreg2,  \tmp2
+        sub             r0,  r0,  r1, lsl #2
+.endif
+        vst1.32         {\dreg1[0]}, [r0,:32], r1
+        vst1.32         {\dreg2[0]}, [r0,:32], r1
+        vst1.32         {\dreg1[1]}, [r0,:32], r1
+        vst1.32         {\dreg2[1]}, [r0,:32], r1
+.endm
+
+@ Round, shift and saturate and store qreg1-4
+.macro do_store qreg1, dreg1, qreg2, dreg2, qreg3, dreg3, qreg4, dreg4, tmp1, tmp2, tmp3, tmp4, type
+        vqrshrun.s16    \dreg1,  \qreg1, #7
+        vqrshrun.s16    \dreg2,  \qreg2, #7
+        vqrshrun.s16    \dreg3,  \qreg3, #7
+        vqrshrun.s16    \dreg4,  \qreg4, #7
+.ifc \type,avg
+        vld1.8          {\tmp1},  [r0,:64], r1
+        vld1.8          {\tmp2},  [r0,:64], r1
+        vld1.8          {\tmp3},  [r0,:64], r1
+        vld1.8          {\tmp4},  [r0,:64], r1
+        vrhadd.u8       \dreg1,  \dreg1,  \tmp1
+        vrhadd.u8       \dreg2,  \dreg2,  \tmp2
+        vrhadd.u8       \dreg3,  \dreg3,  \tmp3
+        vrhadd.u8       \dreg4,  \dreg4,  \tmp4
+        sub             r0,  r0,  r1, lsl #2
+.endif
+        vst1.8          {\dreg1}, [r0,:64], r1
+        vst1.8          {\dreg2}, [r0,:64], r1
+        vst1.8          {\dreg3}, [r0,:64], r1
+        vst1.8          {\dreg4}, [r0,:64], r1
+.endm
+
+@ Evaluate the filter twice in parallel, from the inputs src1-src9 into dst1-dst2
+@ (src1-src8 into dst1, src2-src9 into dst2), adding idx2 separately
+@ at the end with saturation
+.macro convolve dst1, dst2, src1, src2, src3, src4, src5, src6, src7, src8, src9, idx1, idx2, tmp1, tmp2
+        vmul.s16        \dst1, \src1, d0[0]
+        vmul.s16        \dst2, \src2, d0[0]
+        vmla.s16        \dst1, \src2, d0[1]
+        vmla.s16        \dst2, \src3, d0[1]
+        vmla.s16        \dst1, \src3, d0[2]
+        vmla.s16        \dst2, \src4, d0[2]
+.if \idx1 == 3
+        vmla.s16        \dst1, \src4, d0[3]
+        vmla.s16        \dst2, \src5, d0[3]
+.else
+        vmla.s16        \dst1, \src5, d1[0]
+        vmla.s16        \dst2, \src6, d1[0]
+.endif
+        vmla.s16        \dst1, \src6, d1[1]
+        vmla.s16        \dst2, \src7, d1[1]
+        vmla.s16        \dst1, \src7, d1[2]
+        vmla.s16        \dst2, \src8, d1[2]
+        vmla.s16        \dst1, \src8, d1[3]
+        vmla.s16        \dst2, \src9, d1[3]
+.if \idx2 == 3
+        vmul.s16        \tmp1, \src4, d0[3]
+        vmul.s16        \tmp2, \src5, d0[3]
+.else
+        vmul.s16        \tmp1, \src5, d1[0]
+        vmul.s16        \tmp2, \src6, d1[0]
+.endif
+        vqadd.s16       \dst1, \dst1, \tmp1
+        vqadd.s16       \dst2, \dst2, \tmp2
+.endm
+
+@ Load pixels and extend them to 16 bit
+.macro loadl dst1, dst2, dst3, dst4
+        vld1.8          {d2}, [r2], r3
+        vld1.8          {d3}, [r2], r3
+        vld1.8          {d4}, [r2], r3
+.ifnb \dst4
+        vld1.8          {d5}, [r2], r3
+.endif
+        vmovl.u8        \dst1, d2
+        vmovl.u8        \dst2, d3
+        vmovl.u8        \dst3, d4
+.ifnb \dst4
+        vmovl.u8        \dst4, d5
+.endif
+.endm
+
+@ Instantiate a vertical filter function for filtering 8 pixels at a time.
+@ The height is passed in r4 and the width in r5.
+@ idx2 is the index of the largest filter coefficient (3 or 4)
+@ and idx1 is the other one of them.
+.macro do_8tap_8v type, idx1, idx2
+function \type\()_8tap_8v_\idx1\idx2
+        sub             r2,  r2,  r3, lsl #1
+        sub             r2,  r2,  r3
+        vld1.16         {q0},  [r12, :128]
+1:
+        mov             r12,  r4
+
+        loadl           q5,  q6,  q7
+        loadl           q8,  q9,  q10, q11
+2:
+        loadl           q12, q13, q14, q15
+        convolve        q1,  q2,  q5,  q6,  q7,  q8,  q9,  q10, q11, q12, q13, \idx1, \idx2, q4,  q5
+        convolve        q3,  q4,  q7,  q8,  q9,  q10, q11, q12, q13, q14, q15, \idx1, \idx2, q5,  q6
+        do_store        q1,  d2,  q2,  d4,  q3,  d6,  q4,  d8,  d3,  d5,  d7,  d9,  \type
+
+        subs            r12, r12, #4
+        beq             8f
+
+        loadl           q4,  q5,  q6,  q7
+        convolve        q1,  q2,  q9,  q10, q11, q12, q13, q14, q15, q4,  q5,  \idx1, \idx2, q8,  q9
+        convolve        q3,  q8,  q11, q12, q13, q14, q15, q4,  q5,  q6,  q7,  \idx1, \idx2, q9,  q10
+        do_store        q1,  d2,  q2,  d4,  q3,  d6,  q8,  d16, d3,  d5,  d7,  d17, \type
+
+        subs            r12, r12, #4
+        beq             8f
+
+        loadl           q8,  q9,  q10, q11
+        convolve        q1,  q2,  q13, q14, q15, q4,  q5,  q6,  q7,  q8,  q9,  \idx1, \idx2, q12, q13
+        convolve        q3,  q12, q15, q4,  q5,  q6,  q7,  q8,  q9,  q10, q11, \idx1, \idx2, q13, q14
+        do_store        q1,  d2,  q2,  d4,  q3,  d6,  q12, d24, d3,  d5,  d7,  d25, \type
+
+        subs            r12, r12, #4
+        bne             2b
+
+8:
+        subs            r5,  r5,  #8
+        beq             9f
+        @ r0 -= h * dst_stride
+        mls             r0,  r1,  r4, r0
+        @ r2 -= h * src_stride
+        mls             r2,  r3,  r4, r2
+        @ r2 -= 8 * src_stride
+        sub             r2,  r2,  r3, lsl #3
+        @ r2 += 1 * src_stride
+        add             r2,  r2,  r3
+        add             r2,  r2,  #8
+        add             r0,  r0,  #8
+        b               1b
+9:
+        vpop            {q4-q7}
+        pop             {r4-r5}
+        bx              lr
+endfunc
+.endm
+
+do_8tap_8v put, 3, 4
+do_8tap_8v put, 4, 3
+do_8tap_8v avg, 3, 4
+do_8tap_8v avg, 4, 3
+
+@ Instantiate a vertical filter function for filtering a 4 pixels wide
+@ slice. The first half of the registers contain one row, while the second
+@ half of a register contains the second-next row (also stored in the first
+@ half of the register two steps ahead). The convolution does two outputs
+@ at a time; the output of q5-q12 into one, and q4-q13 into another one.
+@ The first half of first output is the first output row, the first half
+@ of the other output is the second output row. The second halves of the
+@ registers are rows 3 and 4.
+@ This only is designed to work for 4 or 8 output lines.
+.macro do_8tap_4v type, idx1, idx2
+function \type\()_8tap_4v_\idx1\idx2
+        sub             r2,  r2,  r3, lsl #1
+        sub             r2,  r2,  r3
+        vld1.16         {q0},  [r12, :128]
+
+        vld1.32         {d2[]},   [r2], r3
+        vld1.32         {d3[]},   [r2], r3
+        vld1.32         {d4[]},   [r2], r3
+        vld1.32         {d5[]},   [r2], r3
+        vld1.32         {d6[]},   [r2], r3
+        vld1.32         {d7[]},   [r2], r3
+        vld1.32         {d8[]},   [r2], r3
+        vld1.32         {d9[]},   [r2], r3
+        vld1.32         {d28[]},  [r2]
+        sub             r2,  r2,  r3, lsl #2
+        sub             r2,  r2,  r3, lsl #1
+        vld1.32         {d2[1]},  [r2], r3
+        vld1.32         {d3[1]},  [r2], r3
+        vmovl.u8        q5,  d2
+        vld1.32         {d4[1]},  [r2], r3
+        vmovl.u8        q6,  d3
+        vld1.32         {d5[1]},  [r2], r3
+        vmovl.u8        q7,  d4
+        vld1.32         {d6[1]},  [r2], r3
+        vmovl.u8        q8,  d5
+        vld1.32         {d7[1]},  [r2], r3
+        vmovl.u8        q9,  d6
+        vld1.32         {d8[1]},  [r2], r3
+        vmovl.u8        q10, d7
+        vld1.32         {d9[1]},  [r2], r3
+        vmovl.u8        q11, d8
+        vld1.32         {d28[1]}, [r2]
+        sub             r2,  r2,  r3
+
+        vmovl.u8        q12, d9
+        vmovl.u8        q13, d28
+
+        convolve        q1,  q2,  q5,  q6,  q7,  q8,  q9,  q10, q11, q12, q13, \idx1, \idx2, q4, q3
+        do_store4       q1,  d2,  q2,  d4,  d3,  d5,  \type
+        subs            r4,  r4,  #4
+        beq             9f
+
+        vld1.32         {d2[]},   [r2], r3
+        vld1.32         {d3[]},   [r2], r3
+        vld1.32         {d4[]},   [r2], r3
+        vld1.32         {d5[]},   [r2], r3
+        sub             r2,  r2,  r3, lsl #1
+        vld1.32         {d2[1]},  [r2], r3
+        vld1.32         {d3[1]},  [r2], r3
+        vmovl.u8        q14, d2
+        vld1.32         {d4[1]},  [r2], r3
+        vmovl.u8        q15, d3
+        vld1.32         {d5[1]},  [r2], r3
+        vmovl.u8        q5,  d4
+        vmovl.u8        q6,  d5
+
+        convolve        q1,  q2,  q9,  q10, q11, q12, q13, q14, q15, q5,  q6,  \idx1, \idx2, q4, q3
+        do_store4       q1,  d2,  q2,  d4,  d3,  d5,  \type
+
+9:
+        vpop            {q4-q7}
+        pop             {r4-r5}
+        bx              lr
+endfunc
+.endm
+
+do_8tap_4v put, 3, 4
+do_8tap_4v put, 4, 3
+do_8tap_4v avg, 3, 4
+do_8tap_4v avg, 4, 3
+
+.macro do_8tap_v_func type, filter, size
+function ff_vp9_\type\()_\filter\()\size\()_v_neon, export=1
+        push            {r4-r5}
+        vpush           {q4-q7}
+        ldr             r4,  [sp, #72]
+        ldr             r5,  [sp, #80]
+        movrel          r12, \filter\()_filter-16
+        add             r12,  r12, r5, lsl #4
+        cmp             r5,  #8
+        mov             r5,  #\size
+.if \size >= 8
+        bge             \type\()_8tap_8v_34
+        b               \type\()_8tap_8v_43
+.else
+        bge             \type\()_8tap_4v_34
+        b               \type\()_8tap_4v_43
+.endif
+endfunc
+.endm
+
+.macro do_8tap_v_filters size
+do_8tap_v_func put, regular, \size
+do_8tap_v_func avg, regular, \size
+do_8tap_v_func put, sharp,   \size
+do_8tap_v_func avg, sharp,   \size
+do_8tap_v_func put, smooth,  \size
+do_8tap_v_func avg, smooth,  \size
+.endm
+
+do_8tap_v_filters 64
+do_8tap_v_filters 32
+do_8tap_v_filters 16
+do_8tap_v_filters 8
+do_8tap_v_filters 4
diff --git a/libavcodec/vp9.h b/libavcodec/vp9.h
index 84bed6d..e4b9f82 100644
--- a/libavcodec/vp9.h
+++ b/libavcodec/vp9.h
@@ -420,7 +420,8 @@  typedef struct VP9Context {
     // whole-frame cache
     uint8_t *intra_pred_data[3];
     VP9Filter *lflvl;
-    DECLARE_ALIGNED(32, uint8_t, edge_emu_buffer)[71 * 80];
+    // This requires 64 + 8 rows, with 80 bytes stride
+    DECLARE_ALIGNED(32, uint8_t, edge_emu_buffer)[72 * 80];
 
     // block reconstruction intermediates
     int16_t *block_base, *block, *uvblock_base[2], *uvblock[2];
@@ -432,6 +433,7 @@  typedef struct VP9Context {
 
 void ff_vp9dsp_init(VP9DSPContext *dsp);
 
+void ff_vp9dsp_init_arm(VP9DSPContext *dsp);
 void ff_vp9dsp_init_x86(VP9DSPContext *dsp);
 
 void ff_vp9_fill_mv(VP9Context *s, VP56mv *mv, int mode, int sb);
diff --git a/libavcodec/vp9block.c b/libavcodec/vp9block.c
index 5a3b356..4a21db3 100644
--- a/libavcodec/vp9block.c
+++ b/libavcodec/vp9block.c
@@ -1176,8 +1176,11 @@  static av_always_inline void mc_luma_dir(VP9Context *s, vp9_mc_func(*mc)[2],
     ff_thread_await_progress(ref_frame, FFMAX(th, 0), 0);
 
     // FIXME bilinear filter only needs 0/1 pixels, not 3/4
+    // The arm/aarch64 _hv filters read one more row than what actually is
+    // needed, so switch to emulated edge one step sooner (!!my * 5) than
+    // horizontally (!!mx * 4).
     if (x < !!mx * 3 || y < !!my * 3 ||
-        x + !!mx * 4 > w - bw || y + !!my * 4 > h - bh) {
+        x + !!mx * 4 > w - bw || y + !!my * 5 > h - bh) {
         s->vdsp.emulated_edge_mc(s->edge_emu_buffer,
                                  ref - !!my * 3 * ref_stride - !!mx * 3,
                                  80,
@@ -1218,8 +1221,11 @@  static av_always_inline void mc_chroma_dir(VP9Context *s, vp9_mc_func(*mc)[2],
     ff_thread_await_progress(ref_frame, FFMAX(th, 0), 0);
 
     // FIXME bilinear filter only needs 0/1 pixels, not 3/4
+    // The arm/aarch64 _hv filters read one more row than what actually is
+    // needed, so switch to emulated edge one step sooner (!!my * 5) than
+    // horizontally (!!mx * 4).
     if (x < !!mx * 3 || y < !!my * 3 ||
-        x + !!mx * 4 > w - bw || y + !!my * 4 > h - bh) {
+        x + !!mx * 4 > w - bw || y + !!my * 5 > h - bh) {
         s->vdsp.emulated_edge_mc(s->edge_emu_buffer,
                                  ref_u - !!my * 3 * src_stride_u - !!mx * 3,
                                  80,
diff --git a/libavcodec/vp9dsp.c b/libavcodec/vp9dsp.c
index af93c0d..0eca389 100644
--- a/libavcodec/vp9dsp.c
+++ b/libavcodec/vp9dsp.c
@@ -2164,6 +2164,8 @@  av_cold void ff_vp9dsp_init(VP9DSPContext *dsp)
     vp9dsp_loopfilter_init(dsp);
     vp9dsp_mc_init(dsp);
 
+    if (ARCH_ARM)
+        ff_vp9dsp_init_arm(dsp);
     if (ARCH_X86)
         ff_vp9dsp_init_x86(dsp);
 }